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| preliminary user?s manual pd780828a subseries 8-bit single-chip microcontroller pd780824a pd780826a pd780828a pd78f0828a document no. u16504ee1v1ud00 date published january 2003 ? nec corporation 2003 printed in germany
2 user?s manual u16504ee1v1ud00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. 3 user ? s manual u16504ee1v1ud00 the information in this document is current as of 28.01, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such nec electronics products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec electronics no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: ? standard ? , ? special ? and ? specific ? . the "specific" quality grade applies only to nec electronics products developed based on a customer- designated ? quality assurance program ? for a specific application. the recommended applications of nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is ? standard ? unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact nec electronics sales representative in advance to determine nec electronics 's willingness to support a given application. notes: 1. " nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. 2. " nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). m8e 02.10 4 user ? s manual u16504ee1v1ud00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa?a madrid, spain tel: 091- 504 27 87 fax: 091- 504 28 60 succursale fran?aise vlizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. singapore tel: 65-6253-8311 fax: 65-6250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos, brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 5 user ? s manual u16504ee1v1ud00 preface readers this manual has been prepared for engineers who want to understand the functions of the pd780828a subseries and design and develop its application systems and programs. pd780828a subseries: pd780824a(a), pd780826a(a), pd780828a(a), pd78f0828a(a), pd780824a(a1), pd780826a(a1), pd780828a(a1), pd780824a(a2), pd780826a(a2), pd780828a(a2) purpose this manual is intended for users to understand the functions of the pd780828a subseries. organization the pd780828a subseries manual is separated into two parts: this manual and the instruction edition (common to the 78k/0 series). pd780828a 78k/0 series subseries user ? s manual this manual instruction pin functions cpu functions internal block functions instruction set interrupt explanation of each instruction other on-chip peripheral functions how to read this manual before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. when you want to use this manual as the manual for (a) products, (a1) products, and (a2) products: when you want to understand the function in general: how to interpret the register format: to make sure the details of the registers when you know the register name. 6 preface user ? s manual u16504ee1v1ud00 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. related documents for pd780828a subseries related documents for development tools (user's manuals) document name document no. japanese english pd780828a subseries user ? s manual planned u16387e 78k/0 series user ? s manual-instruction ieu-849 u12326e 78k/0 series instruction table u10903j - 78k/0 series instruction set u10904j - document name document no. japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k/0 c compiler operation u11517j - language u11518j - cc78k/0 c compiler application note programming note eea-618 eea-1208 cc78k series library source file eeu-777 - ie-78k0-ns-a u14889j u14889e ie-78k0-ns-p04 - u13357e ie-780828-ns-em4 planned np-80gc-tq - - sm78k0 system simulator windows ? base reference u15373j u15373e sm78k0 series system simulator external part user open interface u15802j u15802e id78k0-ns integrated debugger windows base guide u15185j u15185e 7 preface user ? s manual u16504ee1v1ud00 related documents for embedded software (user ? s manual) other documents caution: the above documents are subject to change without prior notice. be sure to use the latest version document when starting design. document name document no. japanese english 78k/0 series real-time os basics u11537j - installation u11536j - technical u11538j - 78k/0 series os mx78k0 basics eeu-5010 - fuzzy knowledge data creation tool eeu-829 eeu1438 78k/0, 78k/ii, 87ad series fuzzy inference development support sys- tem-translator eeu-862 eeu-1444 78k/0 series fuzzy inference development support system- fuzzy inference module eeu-858 eeu-1441 78k/0 series fuzzy inference development support system- fuzzy inference debugger eeu-921 eeu-1458 document name document no. japanese english ic package manual c10943x - semiconductor device mounting technology manual c10535j c10535e quality grade on nec semiconductor devices c11531j c11531e reliability quality control on nec semiconductor devices c10983j c10983e electric static discharge (esd) test mem-539 - semiconductor devices quality assurance guide mei-603 mei-1202 microcontroller related product guide - third party manufacturers u11416j - 8 preface user ? s manual u16504ee1v1ud00 legend symbols and notation are used as follows: weight in data notation : left is high-order column, right is low order column active low notation : xxx (pin or signal name is over-scored) or /xxx (slash before signal name) memory map address: : high order at high stage and low order at low stage note : explanation of (note) in the text caution : item deserving extra attention remark : supplementary explanation to the text numeric notation : binary . . . xxxx or xxx b decimal . . . xxxx hexadecimal . . . xxxx h or 0x xxxx prefixes representing powers of 2 (address space, memory capacity) k (kilo) : 2 10 = 1024 m (mega) : 2 20 = 1024 2 = 1,048,576 g (giga) : 2 30 = 1024 3 = 1,073,741,824 9 user ? s manual u16504ee1v1ud00 table of contents preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 chapter 1 outline (pd780828a subseries) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.2 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4 quality grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.5 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6 78k/0 series expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.8 overview of functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.9 differences between flash and mask rom version . . . . . . . . . . . . . . . . . . . . . . . . . . 33 chapter 2 pin function (pd780828a subseries) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.1 pin function list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.2 non-port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.3 description of pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3.1 p00 to p03 (port 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3.2 p10 to p14 (port 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3.3 p20 to p27 (port 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3.4 p34 to p37 (port 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.3.5 p40 to p47 (port 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.3.6 p50 to p57 (port 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.7 p60 to p65 (port 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.8 p80 to p87 (port 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.3.9 p90 to p97 (port 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.3.10 ctxd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.11 crxd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.12 cclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.13 com0 to com3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.14 v lcd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.15 av dd / av ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.16 av ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.17 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.18 x1 and x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.19 smv dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.20 smv ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.21 v dd0 , v dd1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.3.22 v ss0 , v ss1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.3.23 v pp (pd78f0828a only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.3.24 ic (mask rom version only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.4 pin i/o circuits and recommended connection of unused pins . . . . . . . . . . . . . . . 45 chapter 3 cpu architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1 memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.1 internal program memory space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.1.2 internal data memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1.3 special function register (sfr) area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1.4 data memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2 processor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.2.1 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.2.2 general registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.3 special function register (sfr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.3 instruction address addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.3.1 relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10 user ? s manual u16504ee1v1ud00 3.3.2 immediate addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.3.3 table indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.3.4 register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.4 operand address addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.4.1 implied addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.4.2 register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.4.3 direct addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.4.4 short direct addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.4.5 special function register (sfr) addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.4.6 register indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.4.7 based addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.4.8 based indexed addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.4.9 stack addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 chapter 4 port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.1 port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 4.2 port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 4.2.1 port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.2.2 port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.2.3 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.2.4 port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.2.5 port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.2.6 port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2.7 port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.2.8 port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.2.9 port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3 port function control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.4 port function operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.4.1 writing to input/output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.4.2 reading from input/output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.4.3 operations on input/output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 chapter 5 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.1 clock generator functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.2 clock generator configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.3 clock generator control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.4 system clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.4.1 main system clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.5 clock generator operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.6 changing system clock and cpu clock settings . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.6.1 time required for switchover between system clock and cpu clock . . . . . . . . 110 5.6.2 system clock and cpu clock switching procedure . . . . . . . . . . . . . . . . . . . . . . 111 chapter 6 16-bit timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.1 16-bit timer 2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.2 16-bit timer 2 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.3 16-bit timer 2 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.4 16-bit timer 2 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.4.1 pulse width measurement operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.5 16-bit timer 2 precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 chapter 7 8-bit timer/event counters 50 and 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.1 8-bit timer/event counters 50 and 51 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.1.1 8-bit operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.1.2 16-bit operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.2 8-bit timer/event counters 50 and 51 configurations. . . . . . . . . . . . . . . . . . . . . . . 129 7.3 8-bit timer/event counters 50 and 51 control registers . . . . . . . . . . . . . . . . . . . . 132 7.4 8-bit timer/event counters 50 and 51 operations . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11 user ? s manual u16504ee1v1ud00 7.4.1 interval timer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 7.4.2 external event counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.4.3 square-wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.4.4 pwm output operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 7.5 operation as interval timer (16-bit operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 7.6 cautions on 8-bit timer/event counters 50 and 51 . . . . . . . . . . . . . . . . . . . . . . . . . 153 chapter 8 8-bit timer 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 8.1 8-bit timer 52 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 8.2 8-bit timer 52 configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 8.3 8-bit timer 52 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 8.4 8-bit timer 52 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.4.1 interval timer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 chapter 9 watch timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 9.1 watch timer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 9.2 watch timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 9.3 watch timer mode register (wtm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 9.4 watch timer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.4.1 watch timer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.4.2 interval timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 chapter 10 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10.1 watchdog timer functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10.2 watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.3 watchdog timer control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 10.4 watchdog timer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 10.4.1 watchdog timer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 10.4.2 interval timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 chapter 11 clock output control circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.1 clock output control circuit functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.2 clock output control circuit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.3 clock output function control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 chapter 12 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 12.1 a/d converter functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 12.2 a/d converter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 12.3 a/d converter control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 12.4 a/d converter operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.4.1 basic operations of a/d converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.4.2 input voltage and conversion results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.4.3 a/d converter operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 12.5 a/d converter precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.6 cautions on emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 12.6.1 d/a converter mode register (dam0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 chapter 13 serial interface sio30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 13.1 sio30 functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 97 13.2 sio30 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 13.3 list of sfrs (special function registers). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 13.4 serial interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.5 serial interface operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 13.5.1 operation stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 13.5.2 three-wire serial i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 chapter 14 serial interface sio31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14.1 sio31 functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 05 12 user ? s manual u16504ee1v1ud00 14.2 sio31 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.3 list of sfrs (special function registers). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.4 serial interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 14.5 serial interface operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 14.5.1 operation stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 14.5.2 three-wire serial i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 14.5.3 two-wire serial i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 chapter 15 serial interface channel uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 15.1 uart functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 15.2 uart configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 15.3 list of sfrs (special function registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 15.4 serial interface control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 15.5 serial interface operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 15.5.1 operation stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 15.5.2 asynchronous serial interface (uart) mode . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.6 behavior of uart during standby of the controller . . . . . . . . . . . . . . . . . . . . . . . . 238 chapter 16 can controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16.1 can protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 16.1.1 protocol mode function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 16.1.2 message format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 16.1.3 data frame / remote frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 16.1.4 description of each field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.1.5 error frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 16.1.6 overload frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 16.2 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 16.2.1 arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 16.2.2 bit stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 16.2.3 multi master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 16.2.4 multi cast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 16.2.5 sleep mode/stop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 16.2.6 error control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 16.2.7 baud rate control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 16.2.8 state shift chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 16.3 outline description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1 16.4 connection with target system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.5 can controller configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.6 special function register for can-module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 16.7 message and buffer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 16.8 transmit buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 16.9 transmit message format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 16.10 receive buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 16.11 receive message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 16.12 mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 16.13 operation of the can controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.13.1 can control register (canc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.13.2 dcan error status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 16.13.3 can transmit error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16.13.4 can receive error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16.13.5 message count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 16.14 baudrate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 16.15 function control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 16.15.1 transmit control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 16.15.2 receive control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 16.15.3 mask control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 16.15.4 special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.16 interrupt information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 04 13 user ? s manual u16504ee1v1ud00 16.16.1 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.16.2 transmit interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.16.3 receive interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.16.4 error interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 16.17 influence of the standby function of the can controller . . . . . . . . . . . . . . . . . . . . 306 16.17.1 cpu halt mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 16.17.2 cpu stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 16.17.3 dcan sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 16.17.4 dcan stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 16.18 functional description by flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 16.18.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 16.18.2 transmit preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 16.18.3 abort transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 16.18.4 handling by the dcan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 16.18.5 receive event oriented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 16.18.6 receive task oriented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 chapter 17 lcd controller / driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 17.1 lcd controller/driver functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 17.2 lcd controller/driver configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 17.3 lcd controller/driver control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 17.4 lcd controller/driver settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 17.5 lcd display data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 17.6 common signals and segment signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 17.7 supplying lcd drive voltage v lc0 , v lc1 , and v lc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 17.8 display mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 17.8.1 4-time-division display example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 17.9 cautions on emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 17.9.1 lcd timer control register (lcdtm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 chapter 18 sound generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 18.1 sound generator function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 18.2 sound generator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 18.3 sound generator control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 18.4 sound generator operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 18.4.1 to output basic cycle signal sgof (without amplitude) . . . . . . . . . . . . . . . . . . 335 18.4.2 to output basic cycle signal sgo (with amplitude) . . . . . . . . . . . . . . . . . . . . . 336 chapter 19 meter controller / driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 19.1 meter controller/driver functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 19.2 meter controller/driver configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 19.3 meter controller/driver control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 19.4 meter controller/driver operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19.4.1 basic operation of free-running up counter (smcnt) . . . . . . . . . . . . . . . . . . . 346 19.4.2 update of pwm data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 19.4.3 operation of 1-bit addition circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 19.4.4 pwm output operation (output with 1 clock shifted) . . . . . . . . . . . . . . . . . . . . . 349 chapter 20 interrupt functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 20.1 interrupt function types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 20.2 interrupt sources and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 20.3 interrupt function control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4 interrupt servicing operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 20.4.1 non-maskable interrupt request acknowledge operation . . . . . . . . . . . . . . . . . 361 20.4.2 maskable interrupt request acknowledge operation . . . . . . . . . . . . . . . . . . . . . 363 20.4.3 software interrupt request acknowledge operation . . . . . . . . . . . . . . . . . . . . . 366 20.4.4 multiple interrupt servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 20.4.5 interrupt request reserve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 14 user ? s manual u16504ee1v1ud00 chapter 21 standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21.1 standby function and configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21.1.1 standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21.1.2 standby function control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 21.2 standby function operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 21.2.1 halt mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 21.2.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 chapter 22 reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 22.1 reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 chapter 23 pd78f0828a and memory definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 23.1 memory size switching register (ims) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 23.2 internal expansion ram size switching register . . . . . . . . . . . . . . . . . . . . . . . . . . 389 23.3 self-programming and oscillation control register . . . . . . . . . . . . . . . . . . . . . . . . 390 23.4 flash memory programming with flash programmer. . . . . . . . . . . . . . . . . . . . . . . . 391 23.4.1 selection of transmission method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 23.4.2 initialization of the programming mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 23.4.3 flash memory programming function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 23.4.4 flash programmer connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 23.4.5 flash programming precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 23.5 flash self-programming control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 23.5.1 flash self-programming mode control register . . . . . . . . . . . . . . . . . . . . . . . 395 chapter 24 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 24.1 legends used in operation list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 24.1.1 operand identifiers and description methods . . . . . . . . . . . . . . . . . . . . . . . . . . 397 24.1.2 description of ? operation ? column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 24.2 operation list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399 24.3 instructions listed by addressing type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 chapter 25 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 25.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 25.2 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415 25.3 main system clock oscillation circuit characteristics . . . . . . . . . . . . . . . . . . . . . . 417 25.4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 0 25.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2 25.5.1 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 25.5.2 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 25.5.3 sound generator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 25.5.4 meter controller / driver characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 25.5.5 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 25.5.6 data memory stop mode low supply voltage data retention characteristics 447 25.5.7 flash memory programming characteristics: pd78f0828a(a) . . . . . . . . . . . 450 chapter 26 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 chapter 27 recommended soldering conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 appendix a development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 appendix b embedded software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 appendix c index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 65 appendix d revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 15 user ? s manual u16504ee1v1ud00 list of figures figure 1-1: pin configuration ................................................................................................... ...... 27 figure 1-2: 78k/0 series expansion .............................................................................................. 29 figure 1-3: block diagram ....................................................................................................... ...... 31 figure 2-1: connection of ic pins............................................................................................... ... 44 figure 2-2: pin input/output circuits (1/3) ..................................................................................... 47 figure 3-1: memory map of the pd780824a ............................................................................... 51 figure 3-2: memory map of the pd780826a ............................................................................... 52 figure 3-3: memory map of the pd780828a ............................................................................... 53 figure 3-4: memory map of the pd78f0828a ............................................................................. 54 figure 3-5: data memory addressing of pd780824a ................................................................. 58 figure 3-6: data memory addressing of pd780826a ................................................................. 59 figure 3-7: data memory addressing of pd780828a ................................................................. 60 figure 3-8: data memory addressing of pd78f0828a ............................................................... 61 figure 3-9: program counter configuration .................................................................................. 62 figure 3-10: program status word configuration ........................................................................... 62 figure 3-11: stack pointer configuration........................................................................................ .64 figure 3-12: data to be saved to stack memory............................................................................. 64 figure 3-13: data to be reset to stack memory ............................................................................. 64 figure 3-14: general register configuration ................................................................................... 65 figure 3-15: relative addressing ................................................................................................ .... 70 figure 3-16: immediate addressing............................................................................................... .. 71 figure 3-17: table indirect addressing.......................................................................................... .. 72 figure 3-18: register addressing ................................................................................................ .... 73 figure 3-19: register addressing ................................................................................................ .... 75 figure 3-20: direct addressing .................................................................................................. ...... 76 figure 3-21: short direct addressing ............................................................................................ ... 77 figure 3-22: special-function register (sfr) addressing.............................................................. 78 figure 3-23: register indirect addressing ....................................................................................... .79 figure 3-24: based addressing description example....................................................................... 80 figure 3-25: based indexed addressing description example ......................................................... 81 figure 3-26: stack addressing description example ........................................................................ 82 figure 4-1: port types .......................................................................................................... ......... 83 figure 4-2: p00 to p03 configurations .......................................................................................... 8 7 figure 4-3: p10 to p14 configurations .......................................................................................... 8 8 figure 4-4: p20 to p27 configurations .......................................................................................... 8 9 figure 4-5: p34 to p37 configurations .......................................................................................... 9 0 figure 4-6: p40 to p47 configurations .......................................................................................... 9 1 figure 4-7: p50 to p57 configurations .......................................................................................... 9 2 figure 4-8: p60 to p65 configurations .......................................................................................... 9 3 figure 4-9: p80 to p87 configurations .......................................................................................... 9 4 figure 4-10: p90 to p97 configurations .......................................................................................... 95 figure 4-11: port mode register format ......................................................................................... 9 7 figure 4-12: pull-up resistor option register (pum) format......................................................... 98 figure 4-13: port function register (pf3, pf4, pf8 and pf9) format........................................... 99 figure 5-1: block diagram of clock generator ............................................................................ 103 figure 5-2: processor clock control register format ................................................................. 104 figure 5-3: external circuit of main system clock oscillator ...................................................... 105 figure 5-4: examples of oscillator with bad connection (1/3) .................................................... 106 figure 5-5: system clock and cpu clock switching................................................................... 111 figure 6-1: timer 2 (tm2) block diagram ................................................................................... 113 figure 6-2: 16-bit timer mode control register (tmc2) format ................................................ 116 figure 6-3: capture pulse control register (crc2) format ....................................................... 117 figure 6-4: prescaler mode register (prm2) format ................................................................. 118 figure 6-5: configuration diagram for pulse width measurement by using the free running counter .......................................................................... 119 16 user ? s manual u16504ee1v1ud00 figure 6-6: timing of pulse width measurement operation by using the free running counter and one capture register (with both edges specified).............................. 120 figure 6-7: cr2m capture operation with rising edge specified .............................................. 121 figure 6-8: timing of pulse width measurement operation by free running counter (with both edges specified) ...................................................................................... 122 figure 6-9: 16-bit timer register start timing ............................................................................ 123 figure 6-10: capture register data retention timing................................................................... 123 figure 7-1: 8-bit timer/event counter 50 block diagram............................................................ 129 figure 7-2: 8-bit timer/event counter 51 block diagram............................................................ 130 figure 7-3: block diagram of 8-bit timer/event counters 50 and 51 output control circuit ...... 130 figure 7-4: timer clock select register 50 format..................................................................... 132 figure 7-5: timer clock select register 51 format..................................................................... 133 figure 7-6: 8-bit timer mode control register 50 format........................................................... 134 figure 7-7: 8-bit timer mode control register 51 format (1/2) .................................................. 135 figure 7-8: port mode register 3 format .................................................................................... 136 figure 7-9: port mode register 9 format .................................................................................... 137 figure 7-10: 8-bit timer mode control register settings for interval timer operation ................. 138 figure 7-11: interval timer operation timings (1/3)...................................................................... 139 figure 7-12: 8-bit timer mode control register setting for external event counter operation.... 143 figure 7-13: external event counter operation timings (with rising edge specified) ................. 143 figure 7-14: 8-bit timer mode control register settings for square-wave output operation ..... 144 figure 7-15: square-wave output operation timing ..................................................................... 145 figure 7-16: 8-bit timer control register settings for pwm output operation ............................ 146 figure 7-17: pwm output operation timing (active high setting)................................................. 147 figure 7-18: pwm output operation timings (crn0 = 00h, active high setting) ......................... 147 figure 7-19: pwm output operation timings (crn = ffh, active high setting) ........................... 148 figure 7-20: pwm output operation timings (crn changing, active high setting)....................... 148 figure 7-21: 8-bit timer mode control register settings for 16-bit interval timer operation....... 149 figure 7-22: 16-bit resolution cascade mode (with tm50 and tm51)......................................... 151 figure 7-23: 8-bit timer registers 50 and 51 start timings .......................................................... 153 figure 7-24: external event counter operation timings ............................................................... 153 figure 7-25: timings after compare register change during timer count operation ................. 154 figure 8-1: 8-bit timer/event counter 52 block diagram............................................................ 156 figure 8-2: timer clock select register 52 format..................................................................... 157 figure 8-3: 8-bit timer output control register format.............................................................. 158 figure 8-4: 8-bit timer mode control register settings for interval timer operation ................. 159 figure 8-5: interval timer operation timings (1/3)...................................................................... 159 figure 9-1: block diagram of watch timer.................................................................................. 163 figure 9-2: watch timer mode control register (wtm) format (1/2) ........................................ 165 figure 9-3: operation timing of watch timer/interval timer....................................................... 168 figure 10-1: watchdog timer block diagram................................................................................ 171 figure 10-2: timer clock select register 2 format....................................................................... 172 figure 10-3: watchdog timer mode register format ................................................................... 173 figure 11-1: remote controlled output application example ....................................................... 177 figure 11-2: clock output control circuit block diagram.............................................................. 178 figure 11-3: timer clock select register 0 format....................................................................... 179 figure 11-4: port mode register 6 format .................................................................................... 180 figure 12-1: a/d converter block diagram ................................................................................... 181 figure 12-2: power-fail detection function block diagram .......................................................... 182 figure 12-3: a/d converter mode register (adm1) format.......................................................... 184 figure 12-4: analog input channel specification register (ads1) format ................................... 185 figure 12-5: power-fail compare mode register (pfm) format.................................................. 186 figure 12-6: power-fail compare threshold value register (pft) ................................................... 186 figure 12-7: basic operation of 8-bit a/d converter..................................................................... 187 figure 12-8: relation between analog input voltage and a/d conversion result ........................ 189 figure 12-9: a/d conversion ..................................................................................................... .... 191 figure 12-10: example method of reducing current consumption in standby mode .................... 192 figure 12-11: analog input pin handling ......................................................................................... 193 17 user ? s manual u16504ee1v1ud00 figure 12-12: a/d conversion end interrupt request generation timing....................................... 194 figure 12-13: d/a converter mode register (dam0) format.......................................................... 195 figure 13-1: block diagram of sio30 ............................................................................................ 1 97 figure 13-2: format of serial operation mode register (csim30) ............................................... 199 figure 13-3: format of serial operation mode register (csim30) ............................................... 200 figure 13-4: format of serial operation mode register (csim30) ............................................... 201 figure 13-5: timing of three-wire serial i/o mode........................................................................ 202 figure 14-1: block diagram of sio31 ............................................................................................ 2 06 figure 14-2: format of serial operation mode register (csim31) ............................................... 208 figure 14-3: format of serial mode switch register (sioswi)..................................................... 209 figure 14-4: format of serial operation mode register (csim31) ............................................... 210 figure 14-5: format of serial operation mode register (csim31) ............................................... 211 figure 14-6: format of serial mode switch register (sioswi)..................................................... 212 figure 14-7: format of serial operation mode register (csim31) ............................................... 213 figure 14-8: format of serial mode switch register (sioswi)..................................................... 214 figure 14-9: timing of three-wire serial i/o mode........................................................................ 215 figure 14-10: timing of two-wire serial i/o mode .......................................................................... 215 figure 15-1: block diagram of uart ............................................................................................ 21 7 figure 15-2: format of asynchronous serial interface mode register (asim0) (1/2) ................... 220 figure 15-3: format of asynchronous serial interface status register (asis0) ........................... 222 figure 15-4: format of baud rate generator control register (brgc0) (1/2)............................. 223 figure 15-5: register settings .................................................................................................. ..... 225 figure 15-6: format of asynchronous serial interface mode register (asim0) (1/2) ................... 226 figure 15-7: format of asynchronous serial interface status register (asis0) ........................... 228 figure 15-8: format of baud rate generator control register (brgc0) (1/2)............................. 229 figure 15-9: error tolerance (when k = 0), including sampling errors.......................................... 232 figure 15-10: format of transmit/receive data in asynchronous serial interface......................... 233 figure 15-11: timing of asynchronous serial interface transmit completion interrupt .................. 235 figure 15-12: timing of asynchronous serial interface receive completion interrupt ................... 236 figure 15-13: receive error timing.............................................................................................. ... 237 figure 16-1: data frame ......................................................................................................... ...... 241 figure 16-2: remote frame ....................................................................................................... ... 241 figure 16-3: data frame ......................................................................................................... ...... 242 figure 16-4: arbitration field/standard format mode ................................................................... 242 figure 16-5: arbitration field/extended format mode................................................................... 243 figure 16-6: control field (standard format mode)...................................................................... 244 figure 16-7: control field (extended format mode) ..................................................................... 244 figure 16-8: data field ......................................................................................................... ......... 245 figure 16-9: crc field .......................................................................................................... ........ 245 figure 16-10: ack field ......................................................................................................... ......... 246 figure 16-11: end of frame...................................................................................................... ....... 246 figure 16-12: interframe space/error active ................................................................................... 24 7 figure 16-13: interframe space/error passive ................................................................................ 247 figure 16-14: error frame ....................................................................................................... ........ 248 figure 16-15: overload frame .................................................................................................... .... 249 figure 16-16: nominal bit time (8 to 25 time quanta) ................................................................... 255 figure 16-17: adjusting synchronization of the data bit ................................................................. 256 figure 16-18: bit synchronization............................................................................................... ..... 257 figure 16-19: transmission state shift chart.................................................................................. 25 8 figure 16-20: reception state shift chart ....................................................................................... 259 figure 16-21: error state shift chart ........................................................................................... .... 260 figure 16-22: structural block diagram.......................................................................................... . 261 figure 16-23: connection to the can bus ...................................................................................... 262 figure 16-24: transmit message definition bits ............................................................................. 266 figure 16-25: transmit identifier .............................................................................................. ....... 267 figure 16-26: transmit data .................................................................................................... ....... 268 figure 16-27: control bits for receive identifier ............................................................................. 2 71 figure 16-28: receive status bits (1/2) ........................................................................................ .. 272 18 user ? s manual u16504ee1v1ud00 figure 16-29: receive identifier ............................................................................................... ....... 274 figure 16-30: receive data ..................................................................................................... ....... 275 figure 16-31: identifier compare with mask .................................................................................... 27 7 figure 16-32: control bits for mask identifier ................................................................................. 278 figure 16-33: mask identifier .................................................................................................. ........ 279 figure 16-34: can control register (1/2) ....................................................................................... 280 figure 16-35: dcan support...................................................................................................... ..... 281 figure 16-36: time stamp function ............................................................................................... .283 figure 16-37: sofout toggle function......................................................................................... 283 figure 16-38: global time system function ................................................................................... 283 figure 16-39: can error status register (1/3) ............................................................................... 284 figure 16-40: transmit error counter ........................................................................................... .. 287 figure 16-41: receive error counter ............................................................................................ .. 287 figure 16-42: message count register (mcnt) (1/2) .................................................................... 288 figure 16-43: bit rate prescaler (1/2) ......................................................................................... ... 290 figure 16-44: synchronization control registers 0 and 1 (1/2) ..................................................... 292 figure 16-45: transmit control register (1/2) ................................................................................ 29 6 figure 16-46: receive message register ....................................................................................... 29 8 figure 16-47: mask control register (1/2) ...................................................................................... 299 figure 16-48: redefinition control register (1/2) ........................................................................... 302 figure 16-49: initialization flow chart ......................................................................................... .... 309 figure 16-50: transmit preparation .............................................................................................. ... 310 figure 16-51: transmit abort .................................................................................................... ....... 311 figure 16-52: handling of semaphore bits by dcan-module......................................................... 312 figure 16-53: receive with interrupt, software flow ....................................................................... 313 figure 16-54: receive, software polling......................................................................................... .314 figure 17-1: lcd controller/driver block diagram........................................................................ 316 figure 17-2: lcd clock select circuit block diagram................................................................... 316 figure 17-3: lcd display mode register (lcdm) format ............................................................ 317 figure 17-4: lcd display control register (lcdc) format .......................................................... 318 figure 17-5: relationship between lcd display data memory contents and segment/common outputs319 figure 17-6: common signal waveform........................................................................................ 321 figure 17-7: common signal and segment signal voltages and phases..................................... 321 figure 17-8: example of connection of lcd drive power supply (1/2) ........................................ 322 figure 17-9: 4-time-division lcd display pattern and electrode connections............................ 324 figure 17-10: 4-time-division lcd panel connection example ..................................................... 325 figure 17-11: 4-time-division lcd drive waveform examples (1/3 bias method) ........................ 326 figure 17-12: lcd timer control register (lcdtm) format .......................................................... 327 figure 18-1: sound generator block diagram............................................................................... 329 figure 18-2: concept of each signal ............................................................................................. 330 figure 18-3: sound generator control register (sgcr) format (1/2) ......................................... 331 figure 18-4: sound generator buzzer control register (sgbr) format...................................... 333 figure 18-5: sound generator amplitude register (sgam) format ............................................. 334 figure 18-6: sound generator output operation timing............................................................... 335 figure 18-7: sound generator output operation timing............................................................... 336 figure 19-1: meter controller/driver block diagram...................................................................... 337 figure 19-2: 1-bit addition circuit block diagram .......................................................................... 338 figure 19-3: timer mode control register (mcntc) format........................................................ 341 figure 19-4: compare control register n (mcmpcn) format ...................................................... 342 figure 19-5: port mode control register (pmc) format (1/2)....................................................... 343 figure 19-6: meter controller/driver clock register (smswi) format.......................................... 345 figure 19-7: restart timing after count stop (count start ? count stop ? count start) ........... 346 figure 19-8: update of pwm data ................................................................................................. 347 figure 19-9: timing in 1-bit addition circuit operation .................................................................. 348 figure 19-10: timing of output with 1 clock shifted ....................................................................... 349 figure 20-1: basic configuration of interrupt function (1/2).......................................................... 353 figure 20-2: interrupt request flag register format .................................................................... 356 19 user ? s manual u16504ee1v1ud00 figure 20-3: interrupt mask flag register format......................................................................... 357 figure 20-4: priority specify flag register format........................................................................ 358 figure 20-5: formats of external interrupt rising edge enable register and external interrupt falling edge enable register359 figure 20-6: program status word format ................................................................................... 360 figure 20-7: flowchart from non-maskable interrupt generation to acknowledge ...................... 361 figure 20-8: non-maskable interrupt request acknowledge timing ............................................ 362 figure 20-9: non-maskable interrupt request acknowledge operation ....................................... 362 figure 20-10: interrupt request acknowledge processing algorithm ............................................. 364 figure 20-11: interrupt request acknowledge timing (minimum time).......................................... 365 figure 20-12: interrupt request acknowledge timing (maximum time)......................................... 365 figure 20-13: multiple interrupt example (1/2) ................................................................................ 36 8 figure 20-14: interrupt request hold ............................................................................................ .. 371 figure 21-1: oscillation stabilization time select register format............................................... 374 figure 21-2: standby timing ..................................................................................................... .... 374 figure 21-3: halt mode clear upon interrupt generation ........................................................... 376 figure 21-4: halt mode release by reset input ...................................................................... 377 figure 21-5: stop mode release by interrupt generation .......................................................... 379 figure 21-6: release by stop mode reset input...................................................................... 380 figure 22-1: block diagram of reset function .............................................................................. 381 figure 22-2: timing of reset input by reset input ..................................................................... 382 figure 22-3: timing of reset due to watchdog timer overflow.................................................... 382 figure 22-4: timing of reset input in stop mode by reset input ............................................. 383 figure 23-1: memory size switching register format .................................................................. 388 figure 23-2: internal expansion ram size switching register format......................................... 389 figure 23-3: self-programming and oscillation control register format...................................... 390 figure 23-4: transmission method selection format .................................................................... 391 figure 23-5: connection of using the 3-wire sio30 method ......................................................... 393 figure 23-6: connection of using the 3-wire sio30 method with handshake .............................. 393 figure 23-7: connection of using the uart method ..................................................................... 394 figure 23-8: flash self-programming mode control register format .......................................... 395 figure a-1: development tool configuration ............................................................................... 458 20 user ? s manual u16504ee1v1ud00 21 user ? s manual u16504ee1v1ud00 list of tables table 1-1: the major functional differences between the subseries ............................................... 30 table 1-2: overview of functions ................................................................................................ .... 32 table 1-3: differences between flash and mask rom version ...................................................... 33 table 2-1: pin input/output types............................................................................................... .... 35 table 2-2: non-port pins ........................................................................................................ ......... 37 table 2-3: types of pin input/output circuits.................................................................................. 4 5 table 3-1: internal rom capacities .............................................................................................. .. 55 table 3-2: vectored interrupts .................................................................................................. ....... 56 table 3-3: internal high-speed ram.............................................................................................. .. 57 table 3-4: internal expansion ram (including sharing with dcan) ................................................ 57 table 3-5: special function register list ....................................................................................... .67 table 3-6: implied addressing ................................................................................................... ...... 74 table 3-7: register addressing .................................................................................................. ..... 75 table 3-8: direct addressing.................................................................................................... ........ 76 table 3-9: short direct addressing.............................................................................................. ..... 77 table 3-10: special-function register (sfr) addressing................................................................. 78 table 3-11: register indirect addressing ........................................................................................ ... 79 table 3-12: based addressing.................................................................................................... ....... 80 table 3-13: based indexed addressing ............................................................................................ .81 table 4-1: pin input/output types............................................................................................... .... 84 table 4-2: port configuration................................................................................................... ........ 86 table 5-1: clock generator configuration ..................................................................................... 103 table 5-2: maximum time required for cpu clock switchover ................................................... 110 table 6-1: timer 2 configuration ................................................................................................ ... 114 table 7-1: 8-bit timer/event counter 50 interval times ............................................................... 126 table 7-2: 8-bit timer/event counter 51 interval times ............................................................... 126 table 7-3: 8-bit timer/event counter 50 square-wave output ranges....................................... 127 table 7-4: 8-bit timer/event counter 51 square-wave output ranges....................................... 127 table 7-5: 16-bit timer/event counter tm50/tm51 interval times .............................................. 128 table 7-6: 16-bit timer/event counter tm50/tm51 square-wave output ranges ..................... 128 table 7-7: 8-bit timer/event counters 50 and 51 configurations ................................................. 129 table 7-8: 8-bit timer/event counters 50 interval times.............................................................. 142 table 7-9: 8-bit timer/event counters 51 interval times.............................................................. 142 table 7-10: 8-bit timer/event counters 50 square-wave output ranges ..................................... 145 table 7-11: 8-bit timer/event counters 51 square-wave output ranges ..................................... 145 table 7-12: 8-bit timer/event counters interval times (16-bit timer/event counter mode).......... 152 table 7-13: 8-bit timer/event counter square-wave output ranges (16-bit timer/event counter mode).............................................................................. 152 table 8-1: 8-bit timer 52 interval times ....................................................................................... 1 55 table 8-2: 8-bit timer 52 configurations....................................................................................... 1 55 table 9-1: interval timer interval time......................................................................................... . 164 table 9-2: watch timer configuration........................................................................................... 1 64 table 9-3: interval timer operation............................................................................................. .. 167 table 10-1: watchdog timer inadvertent program overrun detection times ................................ 169 table 10-2: interval times ...................................................................................................... ......... 170 table 10-3: watchdog timer configuration..................................................................................... 171 table 10-4: watchdog timer overrun detection time .................................................................... 174 table 10-5: interval timer interval time........................................................................................ .. 175 table 11-1: clock output control circuit configuration................................................................... 178 table 12-1: a/d converter configuration ........................................................................................ 1 82 table 13-1: composition of sio30 ................................................................................................ .. 198 table 13-2: list of sfrs (special function registers).................................................................... 198 table 14-1: composition of sio31 ................................................................................................ .. 207 table 14-2: list of sfrs (special function registers).................................................................... 207 table 14-3: operating modes and start trigger .............................................................................. 209 22 user ? s manual u16504ee1v1ud00 table 14-4: operating modes and start trigger .............................................................................. 212 table 14-5: operating modes and start trigger .............................................................................. 214 table 15-1: configuration of uart ............................................................................................... .. 218 table 15-2: list of sfrs (special function registers).................................................................... 219 table 15-3: relation between 5-bit counter ? s source clock and ? n ? value .................................... 231 table 15-4: relation between main system clock and baud rate ................................................. 232 table 15-5: causes of receive errors............................................................................................ .237 table 16-1: outline of the function ............................................................................................. .... 239 table 16-2: bit number of the identifier ....................................................................................... ... 243 table 16-3: rtr setting ........................................................................................................ ......... 243 table 16-4: mode setting ....................................................................................................... ........ 243 table 16-5: data length code setting ........................................................................................... 244 table 16-6: operation in the error state ....................................................................................... .. 247 table 16-7: definition of each field ........................................................................................... ..... 248 table 16-8: definition of each frame ........................................................................................... .. 249 table 16-9: arbitration ........................................................................................................ ............ 250 table 16-10: bit stuffing ...................................................................................................... ............. 250 table 16-11: error types ....................................................................................................... ........... 252 table 16-12: output timing of the error frame ................................................................................ 25 2 table 16-13: types of error .................................................................................................... .......... 253 table 16-14: error counter ..................................................................................................... .......... 254 table 16-15: segment name and segment length ......................................................................... 255 table 16-16: can configuration.................................................................................................. ...... 262 table 16-17: sfr definitions.................................................................................................... ......... 263 table 16-18: sfr bit definitions ................................................................................................ ....... 263 table 16-19: message and buffer configuration ............................................................................... 264 table 16-20: transmit message format............................................................................................ 265 table 16-21: receive message format............................................................................................. 270 table 16-22: mask function ...................................................................................................... ........ 276 table 16-23: possible setup of the sofout function..................................................................... 282 table 16-24: transmission / reception flag ..................................................................................... 2 82 table 16-25: possible reactions of the dcan.................................................................................. 287 table 16-26: mask operation buffers............................................................................................. ... 300 table 16-27: interrupt sources .................................................................................................. ........ 304 table 17-1: maximum number of display pixels............................................................................. 315 table 17-2: lcd controller/driver configuration............................................................................. 315 table 17-3: com signals ......................................................................................................... ....... 320 table 17-4: lcd drive voltage................................................................................................... ..... 321 table 17-5: lcd drive voltage supply............................................................................................ 322 table 17-6: selection and non-selection voltages (com0 to com3) ............................................ 324 table 18-1: sound generator configuration.................................................................................... 330 table 18-2: maximum and minimum values of the buzzer output frequency ............................... 332 table 19-1: meter controller/driver configuration........................................................................... 338 table 20-1: interrupt source list ............................................................................................... ...... 352 table 20-2: various flags corresponding to interrupt request sources ........................................ 355 table 20-3: times from maskable interrupt request generation to interrupt service .................... 363 table 20-4: interrupt request enabled for multiple interrupt during interrupt servicing ................. 367 table 21-1: halt mode operating status ...................................................................................... 375 table 21-2: operation after halt mode release ........................................................................... 377 table 21-3: stop mode operating status...................................................................................... 378 table 21-4: operation after stop mode release........................................................................... 380 table 22-1: hardware status after reset ........................................................................................ 3 83 table 23-1: differences among pd78f0828a and mask rom versions...................................... 387 table 23-2: values to be set after reset for the memory size switching register ......................... 388 table 23-3: examples of internal expansion ram size switching register settings ..................... 389 table 23-4: values when the internal expansion ram size switching register is reset .............. 389 table 23-5: transmission method list............................................................................................ .391 table 23-6: main functions of flash memory programming........................................................... 392 23 user ? s manual u16504ee1v1ud00 table 24-1: operand identifiers and description methods .............................................................. 397 table 24-2: operation list ...................................................................................................... ......... 399 table 24-3: 8-bit instructions .................................................................................................. ......... 407 table 24-4: 16-bit instructions ................................................................................................. ........ 408 table 24-5: bit manipulation instructions....................................................................................... .. 408 table 24-6: call/instructions/branch instructions ............................................................................. 40 9 24 user ? s manual u16504ee1v1ud00 25 user ? s manual u16504ee1v1ud00 chapter 1 outline (pd780828a subseries) 1.1 features internal memory instruction execution time can be changed serial interface : 3 channels i/o ports: 59 3-wire mode : 1 channel 8-bit resolution a/d converter: 5 channels 2-wire/3-wire mode : 1 channel sound generator uart mode : 1 channel lcd-controller / driver timer : 6 channels meter controller / driver supply voltage : v dd = 4.0 to 5.5 v can-interface the can macro is qualified according the requirements of iso 11898 using the test procedures defined by iso 16845 and passed successfully the test procedures as recommended by c & s / fh wolfenbuettel. 1.2 application dashboard, climate controller, security unit etc. item program memory (rom) data memory package part number internal high-speed ram lcd display ram internal expansion ram 26 chapter 1 outline (pd780828a subseries) user ? s manual u16504ee1v1ud00 1.3 ordering information remark: xxx indicates rom code suffix. 1.4 quality grade remark: xxx indicates rom code suffix. please refer to "quality grades on nec semiconductor device" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. part number package internal rom pd780824agc(a)-xxx-8bt 80-pin plastic qfp (14 27 chapter 1 outline (pd780828a subseries) user ? s manual u16504ee1v1ud00 1.5 pin configuration (top view) 80-pin plastic qfp (14 figure 1-1: pin configuration cautions: 1. connect ic (internally connected) pin directly to v ss . 2. av dd pin should be connected to v dd . 3. av ss pin should be connected to v ss . remark: when these devices are used in applications, that require reduction of the noise, generated from inside the microcontroller, the implementation of noise reduction measures, such as connecting the v ss0 and v ss1 to different ground lines, is recommended. s15/p80 s16/p97 s17/p96 s18/si31/p95 s19/so31/sio31/p94 s20/sck31/p93 s21/tpo/p92 s22/tio51/p91 s23/ti22/p90 s24/si30/p37 s25/so30/p36 s26/sck30/p35 s27/tio50/p34 ic/vpp x1 x2 v ss 0 v d d 0 ctxd crxd avss ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 av d d /av r ef v ss 1 v d d 1 intp0/p00 intp1/p01 intp2/p02 cclk/p03 ti21/p65 ti20/p64 txd0/p63 rxd0/p62 sgoa/pcl/p61 sgo/sgof/p60 reset smv ss smv d d sm11/p20 sm12/p21 sm13/p22 sm14/p23 sm21/p24 sm22/p25 sm23/p26 sm24/p27 sm31/p50 sm32/p51 sm33/p52 sm34/p53 sm41/p54 sm42/p55 sm43/p56 sm44/p57 smv d d smv ss p81/s14 p82/s13 p83/s12 p84/s11 p85/s10 p86/s9 p87/s8 p40/s7 p41/s6 p42/s5 p43/s4 p44/s3 p45/s2 p46/s1 p47/s0 com3 com2 com1 com0 vlcd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 31 28 chapter 1 outline (pd780828a subseries) user ? s manual u16504ee1v1ud00 pin identifications p00 to p03 : port 0 sgo : sound generator output p10 to p14 : port 1 sgoa : sound generator amplitude p20 to p27 : port 2 sgof : sound generator frequency p34 to p37 : port 3 pcl : programmable clock output p40 to p47 : port 4 sm11 to sm14 : meter controller/driver p50 to p57 : port 5 sm21 to sm24 : meter controller/driver p60 to p65 : port 6 sm31 to sm34 : meter controller/driver p80 to p87 : port 8 sm41 to sm44 : meter controller/driver p90 to p97 : port 9 smv dd : meter controller/driver intp0 to intp2 : interrupt from peripherals smvss : meter controller/driver ti50, ti51 : timer input s0 to s27 : segment output ti20 to ti22 : timer input com0 to com3 : common output to51, to52 : timer output x1, x2 : crystal (main system clock) tpo : timer output reset :reset crxd : can receive data ani0 to ani4 : analog input ctxd : can transmit data av ss : analog ground cclk : can clock av dd /av ref : analog reference voltage and si30, si31 : serial input : adc power supply so30, so31 : serial output v dd0 , v dd1 : power supply sck30 , sck31 :serial clock v pp : programming power supply sio31 : serial input/output v ss0 , v ss1 : ground rxd0 : receive data ic : internally connected txd0 : transmit data : 29 chapter 1 outline (pd780828a subseries) user ? s manual u16504ee1v1ud00 1.6 78k/0 series expansion the following shows the products organized according to usage. the names in the parallelograms are subseries. figure 1-2: 78k/0 series expansion remark: vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same. pd78054 with iebus tm controller pd78054 with enhanced serial i/o pd78078y with enhanced serial i/o and limited function pd78054 with timer and enhanced external interface 64-pin 64-pin 80-pin pd780034a pd780988 pd780034ay 30 chapter 1 outline (pd780828a subseries) user ? s manual u16504ee1v1ud00 the major functional differences between the subseries are shown below. note: 16-bit timer: 2 channels 10-bit timer: 1 channel table 1-1: the major functional differences between the subseries function rom capacity (bytes) timer 8-bit a/d 10-bit a/d 8-bit d/a serial interface i/o v dd min value external expan- sion subseries name 8-bit 16-bit wt wdt control pd78075b 32k to 40k 4 ch 1 ch 1 ch 1 ch 8 ch - 2 ch 3 ch (uart: 1 ch) 88 1.8 v o pd78078 48k to 60k pd78070a - 61 2.7 v pd780058 24k to 60k 2 ch 3 ch (time-divi- sion uart: 1 ch) 68 1.8 v pd780065 40k to 48k - 4 ch (uart: 1 ch) 60 2.7 v pd780078 48k to 60k 2 ch -8 ch 3 ch (uart: 2 ch) 52 1.8 v pd780034a 8k to 32k 1 ch 3 ch (uart: 1 ch) 51 pd780024a 8 ch - pd78083 8k to 16k - - 1 ch (uart: 1 ch) 33 - inverter control pd780988 16k to 60k 3 ch note - 1 ch - 8 ch - 2 ch (uart: 2 ch) 47 4.0 v o vfd drive pd780208 32k to 60k 2 ch 1 ch 1 ch 1 ch 8 ch -- 2 ch 74 2.7 v - pd780232 16k to 24k 3 ch - - 4 ch 40 4.5 v pd78044h 32k to 48k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v pd78044f 16k to 40k 2 ch lcd drive pd780338 48k to 60k 3 ch 2 ch 1 ch 1 ch - 10 ch 1 ch 2 ch (uart: 1 ch) 54 1.8 v - pd780328 62 pd780318 70 pd780308 48k to 60k 2 ch 1 ch 8 ch - - 3 ch (time-divi- sion uart: 1 ch) 57 2.0 v pd78064b 32k 2 ch (uart: 1 ch) pd78064 16k to 32k bus interface supported pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch - - 3 ch (uart: 1 ch) 79 4.0 v o pd78098b 40k to 60k 1 ch 2 ch 69 2.7 v - pd780816 32k to 60k 2 ch 12 ch - 2 ch (uart: 1 ch) 46 4.0 meter control pd780958 48k to 60k 4 ch 2 ch - 1 ch - - - 2 ch (uart: 1 ch) 69 2.2 v - dashboard control pd780852 32k to 40k 3 ch 1 ch 1 ch 1 ch 5 ch - - 3 ch (uart: 1 ch) 56 4.0 v - pd780828a 32k to 60k 59 31 chapter 1 outline (pd780828a subseries) user ? s manual u16504ee1v1ud00 1.7 block diagram figure 1-3: block diagram remark: the internal rom and ram capacity depends on the product. s16/p97 - s23/p90 s23/p37 - s27/p34 com0 - com3 port 0 lcd controller driver standby control 16-bit timer tm2 3 x capture with filter 78k/0 cpu core port 1 port 2 port 3 port 4 port 5 port 6 port 8 tpo21/s21/p92 ti20/p64 tio50/s27/p34 sck30/s26/p35 so30/s25/p36 si30/s24/p37 port 9 s0/p47 - s7/p40 s8/p87 - s15/p80 ti21/p65 ti22/s23/p90 8-bit timer tm50 tio51/s22/p91 8-bit timer tm51 8-bit timer tm52 watch timer serial interface sio30 3-wire mode rxd0/p62 txd0/p63 uart0 pcl/sgoa/p61 clock output control a/d converter ani0/p10 -ani4/p14 av dd /av ref av ss interrupt control intp0/p00 -intp2/p02 ram dcan interface ram interface v dd 0 v dd 1 v ss 0 v ss 1 ic/v pp crxd ctxd system control 4.0 v - 5.5 v x1 x2 reset p00 - p03 p10 - p14 p20 - p27 p34 - p37 p40 - p47 p50 - p57 p60 - p65 p80 - p87 p90 - p97 v lcd sm31/p50 - sm34/p53 sm41/p54 - sm44/p57 meter controller/ driver sm11/p20 - sm14/p23 sm21/p24 - sm24/p27 smv ss smv dd smv dd smv ss watchdog timer power fail detector sgo/sgof/p60 sound generator output rom sck31/s20/p93 so31/sio31/s19/p94 si31/s18/p95 serial interface sio31 3-wire/2-wire mode cclk 32 chapter 1 outline (pd780828a subseries) user ? s manual u16504ee1v1ud00 1.8 overview of functions table 1-2: overview of functions item pd78f0828a pd780828a pd780826a pd780824a rom 59.5 kbytes flash ee 60 kbytes mask rom 48 kbytes mask rom 32 kbytes mask rom hi-speed ram 1024 bytes expansion ram 2016 bytes 480 bytes lcd display ram 28 bytes memory space 64 kbytes general register 8 bits - 32 registers (8 bit x 8 x 4 bank) main system clock 0.25 s/0.5 s/1 s/2 s/4 s (at 8 mhz) instruction set 16-bit operation multiplication/division (8 bits bit manipulation (set, reset, test, boolean operation) bcd adjustment, etc. i/o port 59 in total input ports: 5 output ports: 16 i/o ports: 38 a/d converter 8 bit x 5 channels serial i/f 3-wire mode: 1 channel 2-wire/3-wire mode: 1 channel uart: 1 channel timer 16 bit timer / event counter: 1 channel 8 bit timer / event counter: 2 channels 8 bit interval timer: 1 channel watch timer: 1 channel watchdog timer: 1 channel timer output 3 outputs (8-bit pwm output 33 chapter 1 outline (pd780828a subseries) user ? s manual u16504ee1v1ud00 1.9 differences between flash and mask rom version the differences between the two versions are shown in the table below. differences of the electrical specification are given in the data sheet. table 1-3: differences between flash and mask rom version flash version mask rom version rom flash eeprom mask rom v pp pin yes none (ic pin) internal expansion ram 2016 bytes 480 bytes pd780824a 480 bytes pd780826a 2016 bytes pd780828a 34 user ? s manual u16504ee1v1ud00 [memo] 35 user ? s manual u16504ee1v1ud00 chapter 2 pin function (pd780828a subseries) 2.1 pin function list normal operating mode pins / pin input/output types table 2-1: pin input/output types (1/2) input/output pin name function alternate function after reset input/output p00 port 0 4 bit input / output port input / output mode can be specified bit-wise if used as an input port, a pull-up resistor can be connected by software bit-wise intp0 input p01 intp1 input p02 intp2 input p03 cclk input input p10-p14 port 1 5 bit input port ani0-ani4 input input/output p20 port 2 8 bit output port sm11 hi-z p21 sm12 hi-z p22 sm13 hi-z p23 sm14 hi-z p24 sm21 hi-z p25 sm22 hi-z p26 sm23 hi-z p27 sm24 hi-z input/output p34 port 3 4 bit input / output port input / output mode can be specified bit-wise if used as an input port, a pull-up resistor can be connected by software bit-wise this port can be used as a segment signal output port or an i/o port in 1 bit unit by setting port function ti50/to50/s27 input p35 sck30/s26 input p36 so30/s25 input p37 si30/s24 input input/output p40-p47 port 4 8 bit input / output port input / output mode can be specified bit-wise if used as an input port, a pull-up resistor can be connected by software bit-wise this port can be used as a segment output port or an i/o port, in 8 bit unit by setting port function s0-s7 input input/output p50 port 5 8 bit output port sm31 hi-z p51 sm32 hi-z p52 sm33 hi-z p53 sm34 hi-z p54 sm41 hi-z p55 sm42 hi-z p56 sm43 hi-z p57 sm44 hi-z 36 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 input/output p60 port 6 6 bit input / output port input / output mode can be specified bit-wise if used as an input port, a pull-up resistor can be connected by software bit-wise sgof/sgo input p61 sgoa/pcl input p62 rxd0 input p63 txd0 input p64 ti20 input p65 ti21 input input/output p80-p87 port 7 8 bit input / output port input / output mode can be specified bit-wise if used as an input port, a pull-up resistor can be connected by software bit-wise this port can be used as a segment signal output port or an i/o port in 1 bit units by setting port function s15-s8 input input/output p90 port 9 8 bit input / output port input / output mode can be specified bit-wise if used as an input port, a pull-up resistor can be connected by software bit-wise this port can be used as a segment signal output port or an i/o port in 1 bit units by setting port function ti22/s23 input p91 ti51/to51/s22 input p92 tpo/s21 input p93 sck31/s20 input p94 so31/sio31/s19 input p95 si31/s18 input p96 s17 input p97 s16 input table 2-1: pin input/output types (2/2) input/output pin name function alternate function after reset 37 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 2.2 non-port pins table 2-2: non-port pins (1/2) pin name input/output function after reset alternate function pin intp0 input external interrupts with specifiable valid edges (ris- ing edge, falling edge, both rising and falling edges) input p00 intp1 p01 intp2 p02 si30 input serial interface serial data input input p37/s24 si31 input serial interface serial data input input p95/s18 so30 output serial interface serial data output input p36/s25 so31 output serial interface serial data output input p94/sio31/s19 sck30 input, output serial interface serial clock input / output input p35/s26 sck31 input, output serial interface serial clock input / output input p93/s20 sio31 input, output serial interface serial data input / output input p94/so31/s19 rxd0 input asynchronous serial interface data input input p62 txd0 output asynchronous serial interface data output input p63 crxd input can serial data input input - ctxd output can serial data output output - ti20 input capture trigger input p64 ti21 input capture trigger input p65 ti22 input capture trigger input p90/s23 ti50 input external count clock input to 8-bit timer (tm50) p34/to50/s27 ti51 input external count clock input to 8-bit timer (tm51) p91/to51/s22 tp0 output 16-bit timer output input p92/s21 to50 8-bit timer output (also used for pwm output) p34/ti50/s27 to51 8-bit timer output (also used for pwm output) p91/ti51/s22 pcl output clock output (for main system clock trimming) input p61/sgoa s0-s7 output segment signal output of lcd controller / driver input p40-p47 s8-s15 p80-p87 s16-s17 p97-p96 s18 p95/si31 s19 p94/so31/sio31 s20 p93/sck31 s21 p92/tpo s22 p91/to51/ti51 s23 p90/ti22 s24 p37/si30 s25 p36/so30 s26 p35/sck30 s27 p34/to50/ti50 com0-com3 output common signal output of lcd controller /driver output - 38 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 v lcd - lcd drive voltage - - sgo output sound generator output input p60/sgof sgoa output sound generator amplitude output input p61/pcl sgof output sound generator frequency output input p60/sgo ani0 to ani4 input ad converter analog input input p10-p14 av dd /av ref - ad converter reference voltage input. power supply of the ad converter. -- av ss - ad converter ground potential. connect to v ss -- sm11-sm14 output meter control output hi-z p20-p23 sm21-sm24 p24-p27 sm31-sm34 p50-p53 sm41-sm44 p54-p57 smv dd - meter c/d power supply - - smv ss - meter c/d ground - - reset input system reset input - - x1 - crystal connection for main system clock - - x2 - crystal connection for main system clock - - v dd0 ,v dd1 - positive power supply - - v ss0 ,v ss1 - ground potential - - v pp - high voltage supply for flash programming (only flash version) -ic ic - internal connection. connect directly to v ss (only mask rom version) - v pp table 2-2: non-port pins (2/2) pin name input/output function after reset alternate function pin 39 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 2.3 description of pin functions 2.3.1 p00 to p03 (port 0) this is an 4-bit input/output port. b esides serving as input/output port the external interrupt input is implemented. (1) port mode p00 to p03 function as input/output ports. p00 to p03 can be specified for input or output bit-wise with a port mode register. when they are used as input ports, pull-up resistors can be connected to them by defining the pull-up resistor option register. (2) control mode in this mode this port operates as external interrupt input. (a) intp0 to intp2 intp0 to intp2 are external input pins which can specify valid edges (rising, falling or rising and falling) of this external interrupt pins. (b) cclk cclk is the input pin for an external can clock. 2.3.2 p10 to p14 (port 1) these pins constitute a 5-bit input only port. in addition, they are also used to input a/d converter ana- log signals. the following operating modes can be specified bit-wise. (1) port mode in this mode, p10 to p14 function as a 5-bit input only port. (2) control mode in this mode, p10 to p14 function as a/d converter analog input pins (ani0 to ani4). 2.3.3 p20 to p27 (port 2) these pins constitute an 8-bit output only port. in addition they are also used as pwm output pins to control meters. (1) port mode in this mode, p20 to p27 function as an 8-bit output only port. (2) control mode in this mode, p20 to p27 function as pwm output pins (sm11 to sm14 and sm21 to sm24) for meter control. 40 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 2.3.4 p34 to p37 (port 3) these are 4-bit input/output ports. besides serving as input/output ports, they function as data input/ output to/from and clock input/out of the serial interface. additionally they function as timer input/output and segment signal output of the lcd controller/driver. the port mode and the port function can be specified bit-wise. (1) port mode these ports function as 4-bit input/output ports. they can be specified bit-wise as input or output ports with the port mode register 3. (2) control mode these ports function as timer input/output, as serial interface data input/output, serial clock input/output and as lcd segment output. (a) si30, so30 serial interface serial data input/output pins. (b) sck30 serial interface serial clock input/output pin. (c) ti50 pin for external count clock input to 8-bit timer/event counter. (d) to50 pin for output of the 8-bit timer/event counter. (e) s24 to s27 pins for segment output signals of the lcd controller/driver. caution: when this port is used as a serial interface, the i/o function and output latches must be set according to the function the user requires. 2.3.5 p40 to p47 (port 4) this is an 8-bit input/output port. besides serving as input/output port, they function as segment signal output pins of the lcd controller/driver. the following operating modes can be specified bit-wise or byte-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 4. (2) control mode these port function as segment output signal pins (s0 to s7) of the lcd controller/driver and can specified byte-wise. 41 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 2.3.6 p50 to p57 (port 5) these pins constitute an 8-bit output only port. in addition they also function as pwm output pins to control meters. (1) port mode in this mode, p50 to p57 function as an 8-bit output only port. (2) control mode in this mode, p50 to p57 function as pwm output pins (sm31 to sm34 and sm41 to sm44) for meter control. 2.3.7 p60 to p65 (port 6) these are 6-bit input/output ports. beside serving as input/output ports, they function as timer input, clock output, sound generator output and as input/output of the asynchronous serial interface. the following operating modes can be specified bit-wise. (1) port mode these ports function as 5-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 3. (2) control mode these ports function as timer input, clock output, as input/output of the asynchronous serial inter- face and sound generator output. (a) ti20, ti21 pins for external capture trigger input to the 16-bit timer capture registers of tm2. (b) pcl clock output pin. (c) sgo, sgoa and sgof pins for separate or composed signal output of the sound generator. (d) (e) rxd0, txd0 asynchronous serial interface data input/output pins. caution: when this port is used as a serial interface, the i/o function and output latches must be set according to the function the user requires. 42 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 2.3.8 p80 to p87 (port 8) these are 8-bit input/output ports. besides serving as input/output ports, they function as segment signal output pins of the lcd controller/driver. the following operating modes can be specified bit-wise or byte-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 8. (2) control mode these ports function as segment output signal pins (s8 to s15) of the lcd controller/driver. 2.3.9 p90 to p97 (port 9) these are 8-bit input/output ports. besides serving as input/output ports, they function as segment sig- nal output pins of the lcd controller/driver, timer input/output and as input/output of the serial interface. the following operating modes can be specified bit-wise or byte-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 9. (2) control mode these ports function as timer input/output, timer capture input, as timer output and as lcd seg- ment output. (a) ti22 pin for external capture trigger input to the 16-bit timer capture register of tm2. (b) tpo pin for output of the 16-bit timer (tm2). (c) ti51 pin for external count clock input to 8-bit timer/event counter. (d) to51 pin for output of the 8-bit timer/event counter. (e) s16 to s23 pins for segment output signals of the lcd controller/driver. (f) sck31 serial interface serial clock input/output pin. (g) si31, so31, sio31 serial interface serial data input/output pins. 43 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 2.3.10 ctxd this pin functions as can-controller transmit output. 2.3.11 crxd this pin functions as can-controller receive input. 2.3.12 cclk this pin functions as external can-controller clock input. 2.3.13 com0 to com3 these are lcd controller/driver common signal output pins. they output common signals under the fol- lowing condition: - 4-time-division is performed in 1/3 bias mode. 2.3.14 v lcd this pin supplies a voltage to drive an lcd. 2.3.15 av dd / av ref a/d converter reference voltage input pin and the power supply for the a/d-converter. when a/d con- verter is not used, connect this pin to v dd . 2.3.16 av ss this is a ground voltage pin of a/d converter. always use the same voltage as that of the v ss pin even when a/d converter is not used. 2.3.17 reset this is a low-level active system reset input pin. 2.3.18 x1 and x2 crystal resonator connect pins for main system clock oscillation. for external clock supply, input it to x1. 2.3.19 smv dd this pin supplies a positive power to the meter controller/driver. 2.3.20 smv ss this is the ground pin of the meter controller/driver. 44 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 2.3.21 v dd0 , v dd1 v dd0 is the positive power supply pin for ports. v dd1 is the positive power supply pin for blocks other than ports. 2.3.22 v ss0 , v ss1 v ss0 is the ground pin for ports. v ss1 is the ground pin for blocks other than ports. 2.3.23 v pp (pd78f0828a only) high-voltage apply pin for flash programming mode setting. connect this pin directly to v ss in normal operating mode. 2.3.24 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the pd78f0828a at delivery. connect it directly to the v ss with the shortest possible wire in the normal operating mode. when a voltage difference is produced between the ic pin and v ss pin because the wiring between those two pins is too long or an external noise is input to the ic pin, the user ? s program may not run nor- mally. figure 2-1: connection of ic pins caution: connect ic pins to v ss pins directly. vic as short as possible ss 45 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 2.4 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in the following table. for the input/output circuit configuration of each type, see ttable 2-3, ? types of pin input/output cir- cuits, ? on page 45. table 2-3: types of pin input/output circuits (1/2) pin name input/output circuit type i/o recommended connection for unused pins p00/intp0 8-a i/o input: connect to v dd or v ss via a resistor individually. output: leave open. p01/int01 p02/int02 p03/cclk p10/ani0 9i connect to v dd or v ss directly p11/ani1 p12/ani2 p13/ani3 p14/ani4 p20/sm11 4 o leave open. p21/sm12 p22/sm13 p23/sm14 p24/sm21 p25/sm22 p26/sm23 p27/sm24 p34/ti50/to50/s27 17-b i/o input: connect to v dd or v ss via a resistor individually. output: leave open. p35/sck30 /s26 p36/so30/s25 17-a p37/si30/s24 17-b p40/s7 17-a i/o input: connect to v dd or v ss via a resistor individually. output: leave open. p41/s6 p42/s5 p43/s4 p44/s3 p45/s2 p46/s1 p47/s0 46 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 p50/sm31 4 o leave open. p51/sm32 p52/sm33 p53/sm34 p54/sm41 p55/sm42 p56/sm43 p57/sm44 p60/sgof/sgo 5 i/o input: connect to v dd or v ss via a resistor individually. output: leave open. p61/rcl/sgoa 5 p62/rxd0 8 p63/txd0 5 p64/ti20 8 p65/ti21 8 p80/s15 17-b i/o input: connect to v dd or v ss via a resistor individually. output: leave open. p81/s14 p82/s13 p83/s12 p84/s11 p85/s10 p86/s9 p87/s8 p90/ti22/s23 17-b i/o input: connect to v dd or v ss via a resistor individually. output: leave open. p91/ti51/to50/s22 17-b p92/tpo/s21 17-a p93/sck31 /s20 17-b p94/so31/sio31/s19 p95/si31/s18 p96/s17 p97/s16 com0-com3 18 o leave open v lcd -- connect to v ss crxd 1 i connect to v dd ctxd 2 o leave open. reset 1i- av dd / av ref -- connect to v dd av ss -- connect to v ss ic -- connect directly to v ss v pp table 2-3: types of pin input/output circuits (2/2) pin name input/output circuit type i/o recommended connection for unused pins 47 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 figure 2-2: pin input/output circuits (1/3) type 1 in type 4 data output disable v p-ch n-ch out dd type 2 data v p-ch n-ch out dd type 5 data output disable v p-ch n-ch in/out dd input disable type 8-a pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd data output disable v p-ch n-ch in/out dd type 8 48 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 figure 2-2: pin input/output circuits (2/3) type 9 p-ch n-ch input enable + - v ref (threshold voltage) in comparator type 17 out p-ch p-ch n-ch p-ch n-ch n-ch v lc0 v lc1 v lc2 seg data type 17-a type 17-b pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd input enable p-ch p-ch n-ch p-ch n-ch n-ch v lc0 v lc1 v lc2 seg data pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd p-ch p-ch n-ch p-ch n-ch n-ch v lc0 v lc1 v lc2 seg data 49 chapter 2 pin function (pd780828a subseries) user ? s manual u16504ee1v1ud00 figure 2-2: pin input/output circuits (3/3) type 18 p-ch n-ch v lc0 v lc1 v lc2 com out 50 user ? s manual u16504ee1v1ud00 [memo] 51 user ? s manual u16504ee1v1ud00 chapter 3 cpu architecture 3.1 memory space the memory map of the pd780824a is shown in figure 3-1. figure 3-1: memory map of the pd780824a note: in the expansion ram between f600h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fa80h fa7fh fee0h fedfh 0000h 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h lcd display ram 28 x 4 bits expansion ram 480 bytes program area callf entry area program area callt table area vector table area special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal rom 32 kbytes not usable not usable not usable ff20h ff1fh fe20h fa64h fa63h faffh f7e0h f7dfh f600h f5ffh 8000h 7fffh fb00h (shared with dcan) 52 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 the memory map of the pd780826a is shown in figure 3-2. figure 3-2: memory map of the pd780826a note: in the expansion ram between f600h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fa80h fa7fh fee0h fedfh 0000h bfffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h lcd display ram 28 x 4 bits expansion ram 480 bytes (shared with dcan) program area callf entry area program area callt table area vector table area special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal rom 48 kbytes not usable not usable not usable ff20h ff1fh fe20h fa64h fa63h faffh f7e0h f7dfh f600h f5ffh c000h bfffh fb00h 53 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 the memory map of the pd780828a is shown in figure 3-3. figure 3-3: memory map of the pd780828a notes: 1. in the expansion ram between f000h and f3ffh it is possible to do code execution. 2. in the expansion ram between f400h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fa80h fa7fh fee0h fedfh 0000h efffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h lcd display ram 28 x 4 bits expansion ram 480 bytes (shared with dcan) program area callf entry area program area callt table area vector table area special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal rom 60 kbytes not usable not usable ff20h ff1fh fe20h fa64h fa63h faffh f7e0h f7dfh f600h f5ffh f000h efffh expansion ram 512 bytes fb00h expansion ram 1024 bytes f400h f3ffh 54 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 the memory map of the pd78f0828a is shown in figure 3-4. figure 3-4: memory map of the pd78f0828a notes: 1. in the expansion ram between f000h and f5ffh it is possible to do code execution. 2. in the expansion ram between f600h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fa80h fa7fh fee0h fedfh 0000h edffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h lcd display ram 28 x 4 bits expansion ram 480 bytes (shared with dcan) program area callf entry area program area callt table area vector table area special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal rom 59.5 kbytes not usable not usable ff20h ff1fh fe20h fa64h fa63h faffh f7e0h f7dfh f600h f5ffh ee00h edffh expansion ram 1536 bytes f000h efffh not usable fb00h 55 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.1.1 internal program memory space the internal program memory space stores programs and table data. this is generally accessed by the program counter (pc). the pd780828a subseries have various size of internal roms or flash eprom as shown below. the internal program memory is divided into three areas: vector table area, callt instruction table area, and callf instruction table area. these areas are described on the next page. table 3-1: internal rom capacities part number internal rom ty p e c a p a c i t y pd780824a mask rom 32768 x 8-bits pd780826a mask rom 49152 x 8-bits pd780828a mask rom 61440 x 8-bits pd78f0828a flash eeprom 60928 x 8-bits 56 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the reset input and pro- gram start addresses for branch upon generation of each interrupt request are stored in the vector table area. of the 16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses. (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruc- tion (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf). table 3-2: vectored interrupts vector table address interrupt request 0004h inwdt 0006h intad 0008h intovf 000ah inttm20 000ch inttm21 000eh inttm22 0010h intp0 0012h intp1 0014h intp2 0016h intce 0018h intcr 001ah intct0 001ch intct1 001eh intcsi30 0020h intser0 0022h intsr0 0024h intst0 0026h inttm50 0028h inttm51 002ah inttm52 002eh intwti 0030h intwt 0032h intcsi31 003eh brk 57 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.1.2 internal data memory space the pd780828a subseries units incorporate the following rams. (1) internal high-speed ram the 32-byte area fee0h to feff is allocated with four general purpose register banks composed of eight 8-bit registers. the internal high-speed ram has to be used as stack memory. (2) lcd-display ram buffer ram is allocated to the 28 x 4 bits area from fa64h to fa7fh. lcd-display ram can also be used as normal ram. (3) internal expansion ram (including sharing with dcan) 3.1.3 special function register (sfr) area an on-chip peripheral hardware special function register (sfr) is allocated in the area ff00h to ffffh. (refer to table 3-5, ? special function register list, ? on page 67 ). caution: do not access addresses where the sfr is not assigned. table 3-3: internal high-speed ram device internal high speed ram pd780824a 1024 x 8 bits (fb00h to feffh) pd780826a 1024 x 8 bits (fb00h to feffh) pd780828a 1024 x 8 bits (fb00h to feffh) pd78f0828a 1024 x 8 bits (fb00h to feffh) table 3-4: internal expansion ram (including sharing with dcan) device internal expansion ram pd780824a 480 x 8 bits (f600h to f7dfh) pd780826a 480 x 8 bits (f600h to f7dfh) pd780828a 2016 x 8 bits (f000h to f7dfh) pd78f0828a 2016 x 8 bits (f000h to f7dfh) 58 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.1.4 data memory addressing the pd780828a subseries is provided with a verity of addressing modes which take account of mem- ory manipulability, etc. special addressing methods are possible to meet the functions of the special function registers (sfrs) and general registers. the data memory space is the entire 64k-byte space (0000h to ffffh). figures 3-5 to 3-8 show the data memory addressing modes. for details of addressing, refer to 3.4 ? operand address addressing ? on page 74 . figure 3-5: data memory addressing of pd780824a note: in the expansion ram between f600h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fa80h fa7fh fee0h fedfh 8000h 7fffh 0000h lcd display ram 28 x 4 bits expansion ram 480 x 8 bits (shared with dcan) special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal mask rom 32768 x 8 bits not usable not usable not usable ff20h ff1fh fe20h fa64h fa63h fb00h faffh f7e0h f7dfh f600h f5ffh sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing 59 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 figure 3-6: data memory addressing of pd780826a note: in the expansion ram between f600h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fa80h fa7fh fee0h fedfh c000h bfffh 0000h lcd display ram 28 x 4 bits expansion ram 480 x 8 bits (shared with dcan) special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal mask rom 49152 x 8 bits not usable not usable not usable ff20h ff1fh fe20h fa64h fa63h fb00h faffh f7e0h f7dfh f600h f5ffh sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing 60 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 figure 3-7: data memory addressing of pd780828a notes: 1. in the expansion ram between f000h and f3ffh it is possible to do code execution. 2. in the expansion ram between f400h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fa80h fa7fh fee0h fedfh f000h efffh 0000h lcd display ram 28 x 4 bits expansion ram 480 x 8 bits (shared with dcan) special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal mask rom 61440 x 8 bits not usable not usable ff20h ff1fh fe20h fa64h fa63h fb00h faffh f7e0h f7dfh f600h f5ffh sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing expansion ram 512 x 8 bits expansion ram 1024 x 8 bits f400h f3ffh 61 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 figure 3-8: data memory addressing of pd78f0828a notes: 1. in the expansion ram between f000h and f5ffh it is possible to do code execution. 2. in the expansion ram between f600h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fa80h fa7fh fee0h fedfh ee00h edffh 0000h lcd display ram 28 x 4 bits expansion ram 480 x 8 bits (shared with dcan) special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits flash eeprom 60928 x 8 bits not usable not usable ff20h ff1fh fe20h fa64h fa63h fb00h faffh f7e0h f7dfh f600h f5ffh sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing expansion ram 1536 x 8 bits not usable f000h efffh 62 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.2 processor registers the pd780828a subseries units incorporate the following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses, and stack memory. the control registers consist of a program counter, a program status word and a stack pointer. (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register con- tents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-9: program counter configuration (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruc- tion execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 3-10: program status word configuration pc 15 0 ie 7 0 z rbs1 rbs0 ac 0 isp cy 63 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledge operations of the cpu. when 0, the ie is set to interrupt disabled (di) status. all interrupts except non-maskable interrupt are disabled. when 1, the ie is set to interrupt enabled (ei) status and interrupt request acknowledge is control- led with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources, and a priority specification flag. the ie is reset to (0) upon di instruction execution or interrupt request acknowledgement and is set to (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information which indicates the register bank selected by sel rbn instruc- tion execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledge able maskable vectored interrupts. when 0, acknowledgment of the vectored interrupt request specified to low-order priority with the priority specify flag registers (pr0l, pr0h, and pr1l) is disabled. whether an actual interrupt request is acknowledged or not is controlled with the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift- out value upon rotate instruction execution and functions as a bit accumulator during bit manipula- tion instruction execution. 64 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high- speed ram area can be set as the stack area. figure 3-11: stack pointer configuration the sp is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. each stack operation saves/resets data as shown in figures 3-12 and 3-13. caution: since reset input makes sp contents indeterminate, be sure to initialize the sp before instruction execution. figure 3-12: data to be saved to stack memory figure 3-13: data to be reset to stack memory sp 15 0 interrupt and brk instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp _ 2 sp _ 2 register pair upper call, callf, and callt instruction push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 reti and retb instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp + 2 sp register pair upper ret instruction pop rp instruction sp + 1 pc7 to pc0 sp sp + 2 sp sp + 1 sp + 2 sp sp + 1 sp sp + 3 65 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.2.2 general registers a general register is mapped at particular addresses (fee0h to feffh) of the data memory. it consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can also be used as an 8-bit register. two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de, and hl). they can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank. figure 3-14: general register configuration (a) absolute name (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fee0h fee8h bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h 66 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.2.3 special function register (sfr) unlike a general register, each special function register has special functions. it is allocated in the ff00h to ffffh area. the special function registers can be manipulated in a similar way as the general registers, by using operation, transfer, or bit-manipulate instructions. the special function registers are read from and writ- ten to in specified manipulation bit units (1, 8, and/or 16) depending on the register type. each manipulation bit unit can be specified as follows. 1-bit manipulation describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. 8-bit manipulation describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. 16-bit manipulation describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, describe an even address. table 3-5, ? special function register list, ? on page 67 gives a list of special function regis- ters. the meaning of items in the table is as follows. symbol the assembler software ra78k0 translates these symbols into corresponding addresses where the special function registers are allocated. these symbols should be used as instruction operands in the case of programming. r/w this column shows whether the corresponding special function register can be read or written. r/w : both reading and writing are enabled. r : the value in the register can read out. a write to this register is ignored. w : a value can be written to the register. reading values from the register is impossible. manipulation the register can be manipulated in bit units. after reset the register is set to the value immediately after the reset signal is input. 67 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 table 3-5: special function register list (1/3) address sfr name symbol r/w manipulation bit unit after reset 1-bit 8-bit 16-bit ff00h port 0 p0 r/w 68 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 ff66h prescaler mode register 2 prm2 r/w - table 3-5: special function register list (2/3) address sfr name symbol r/w manipulation bit unit after reset 1-bit 8-bit 16-bit 69 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 note: the values after reset depend on the product (see table 23-4, ? values when the internal expansion ram size switching register is reset, ? on page 389). ffb9h synchronous control register 0 sync0 r/w - table 3-5: special function register list (3/3) address sfr name symbol r/w manipulation bit unit after reset 1-bit 8-bit 16-bit 70 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. however, when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing. (for details of instructions, refer to 78k/0 user's manual - instructions (u12326e) . 3.3.1 relative addressing the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed two ? s complement data (-128 to +127) and bit 7 becomes a sign bit. in other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. figure 3-15: relative addressing 15 0 pc + 15 0 876 s 15 0 pc a jdisp8 when s = 0, all bits of a are 0. when s = 1, all bits of a are 1. pc indicates the start address of the instruction after the br instruction. ... 71 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.3.2 immediate addressing immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call!addr16 or br!addr16 or callf!addr11 instruction is exe- cuted. call!addr16 and br!addr16 instructions can branch to all the memory space. callf!addr11 instruction branches to the area from 0800h to 0fffh. figure 3-16: immediate addressing (a) in the case of call!addr16 and br!addr16 instructions (b) in the case of callf!addr11 instruction 15 0 pc 87 70 call or br low addr. high addr. 15 0 pc 87 70 fa 10 ? 8 11 10 00001 643 callf fa 7 ? 0 72 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.3.3 table indirect addressing table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. table indirect addressing is carried out when the callt [addr5] instruction is executed. this instruction can refer to the address stored in the memory table 40h to 7fh and branch to all the memory space. figure 3-17: table indirect addressing 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4 ? 0 operation code 73 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.3.4 register addressing register pair (ax) contents to be specified with an instruction word are transferred to the program coun- ter (pc) and branched. this function is carried out when the br ax instruction is executed. figure 3-18: register addressing rp 15 0 pc 87 7 7 00 a x 74 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.4 operand address addressing the following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 implied addressing the register which functions as an accumulator (a and ax) in the general register is automatically (implicitly) addressed. of the pd780828a subseries instruction words, the following instructions employ implied addressing. operand format because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. description example in the case of mulu x with an 8-bit x 8-bit multiply instruction, the product of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing. table 3-6: implied addressing instruction register to be specified by implied addressing mulu a register for multiplicant and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values which become decimal correction targets ror4/rol4 a register for storage of digit data which undergoes digit rotation 75 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.4.2 register addressing the general register is accessed as an operand. the general register to be accessed is specified with register bank select flags (rbs0 and rbs1) and register specify code (rn, rpn) in the instruction code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. operand format ? r ? and ? rp ? can be described with function names (x, a, c, b, e, d, l, h, ax, bc, de and hl) as well as absolute names (r0 to r7 and rp0 to rp3). description example figure 3-19: register addressing (a) mov a, c; when selecting c register as r (b) incw de; when selecting de register pair as rp table 3-7: register addressing identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl 01100010 register specify code operation code 10000100 register specify code operation code 76 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.4.3 direct addressing the memory indicated by immediate data in an instruction word is directly addressed. operand format description example mov a, !0fe00h; when setting !addr16 to fe00h figure 3-20: direct addressing table 3-8: direct addressing identifier description addr16 label or 16-bit immediate data operation code 10001110 op code 00000000 00h 11111110 feh 77 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.4.4 short direct addressing the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. the fixed space to which this addressing is applied to is the 256-byte space, from fe20h to ff1fh. an internal high-speed ram and a special function register (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area where short direct addressing is applied (ff00h to ff1fh) is a part of the sfr area. in this area, ports which are frequently accessed in a program, a compare register of the timer/event counter, and a capture register of the timer/event counter are mapped and these sfrs can be manipu- lated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to figure 3-21 below. operand format figure 3-21: short direct addressing (a) description example mov 0fe30h, #50h; when setting saddr to fe30h and immediate data to 50h. (b) illustration table 3-9: short direct addressing identifier description saddr label of fe20h to ff1fh immediate data saddrp label of fe20h to ff1fh immediate data (even address only) operation code 00010001 op code 00110000 30h (saddr-offset) 01010000 50h (immediate data) when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset 78 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.4.5 special function register (sfr) addressing the memory-mapped special function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfr mapped at ff00h to ff1fh can be accessed with short direct addressing. operand format figure 3-22: special-function register (sfr) addressing (a) description example mov pm0, a; when selecting pm0 (fe20h) as sfr (b) illustration table 3-10: special-function register (sfr) addressing identifier description sfr special-function register name sfrp 16-bit manipulatable special-function register name (even address only) operation code 11110110 op code 00100000 20h (sfr-offset) 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 79 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.4.6 register indirect addressing the memory is addressed with the contents of the register pair specified as an operand. the register pair to be accessed is specified with the register bank select flag (rbs0 and rbs1) and the register pair specify code in the instruction code. this addressing can be carried out for all the memory spaces. operand format figure 3-23: register indirect addressing (a) description example mov a, [de]; when selecting [de] as register pair (b) illustration table 3-11: register indirect addressing identifier description - [de], [hl] operation code 10000101 16 0 8 d 7 e memory the contents of addressed memory are transferred memory address specified by register pair de 7 a de 0 0 7 80 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.4.7 based addressing 8-bit immediate data is added to the contents of the base register, that is, the hl register pair, and the sum is used to address the memory. the hl register pair to be accessed is in the register bank speci- fied with the register bank select flags (rbs0 and rbs1). addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. operand format figure 3-24: based addressing description example mov a, [hl + 10h]; when setting byte to 10h table 3-12: based addressing identifier description [hl + byte] operation code 10101110 00010000 81 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.4.8 based indexed addressing the b or c register contents specified in an instruction are added to the contents of the base register, that is, the hl register pair, and the sum is used to address the memory. the hl, b, and c registers to be accessed are registers in the register bank specified with the register bank select flag (rbs0 and rbs1). addition is performed by expanding the contents of the b or c register as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. operand format figure 3-25: based indexed addressing description example in the case of mov a, [hl + b] table 3-13: based indexed addressing identifier description [hl + b], [hl + c] operation code 10101011 82 chapter 3 cpu architecture user ? s manual u16504ee1v1ud00 3.4.9 stack addressing the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing enables to address the internal high-speed ram area only. figure 3-26: stack addressing description example in the case of push de operation code 10110101 83 user ? s manual u16504ee1v1ud00 chapter 4 port functions 4.1 port functions the pd780828a subseries units incorporate five input ports and thirty-eight input/output ports. figure 4-1 shows the port configuration. every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. besides port functions, the ports can also serve as on- chip hardware input/output pins. figure 4-1: port types port 0 port 6 port 2 p00 p60 p65 p10 p03 p14 p20 p27 port 3 port 5 p80 p87 port 8 p34 p37 p50 p57 p90 p97 port 9 port 4 p40 p47 port 1 84 chapter 4 port functions user ? s manual u16504ee1v1ud00 table 4-1: pin input/output types (1/2) input/ output pin name function alternate function after reset input/ output p00 port 0 4-bit input/output port input/output mode can be specified bit-wise if used an input port, a pull-up resistor can be connected by software bit-wise intp0 input p01 intp1 input p02 intp2 input p03 cclk input input p10-p14 port 1 5-bit input only port an10-an17 input output p20 port 2 8-bit output only port sm11 output p21 sm12 hi-z p22 sm13 p23 sm14 p24 sm21 p25 sm22 p26 sm23 p27 sm24 input/ output p34 port 3 4 bit input/output port input/output mode can be specified bit-wise ti50/to50/s27 input p35 sck30 /s26 input p36 s030/s25 input p37 si30/s24 input input/ output p40-p47 port 4 8-bit input/output port input/output mode can be specified bit-wise this port can be used as a segment signal output port or an i/o port, in an 8-bit unit setting the port function s0-s7 input output p50 port 5 8-bit output only port sm31 hi-z p51 sm32 p52 sm33 p53 sm34 p54 sm41 p55 sm42 p56 sm43 p57 sm44 input/ output p60 port 6 6-bit input/output port input/output mode can be specified bit-wise sgof-sgo input p61 sgoa-pcl p62 rxd0 p63 txd0 p64 ti20 p65 ti21 85 chapter 4 port functions user ? s manual u16504ee1v1ud00 input/ output p80-p87 port 8 8-bit input/output port input/output mode can be specified bit-wise if used an input port, a pull-up resistor can be connected by software this port can be used as a segment signal output port or an i/o port, in an 1-bit units by setting the port function s15-s8 input input/ output p90 port 9 8-bit input/output port input/output mode can be specified bit-wise this port can be used as a segment signal output port or an i/o port, in an 1-bit units by setting the lcd control register ti22/s23 input p91 to51/ti51/s22 p92 tp0/s21 p93 sck31 /s20 p94 so31/sio31/s19 p95 si31/s18 p96 s17 p97 s16 table 4-1: pin input/output types (2/2) input/ output pin name function alternate function after reset 86 chapter 4 port functions user ? s manual u16504ee1v1ud00 4.2 port configuration a port consists of the following hardware: table 4-2: port configuration item configuration control register port mode register (pmm: m = 0, 2 to 6, 8, 9) pull-up resistor option register (pum: m = 0, 3, 4, 6, 8, 9) port function register (pfm: m = 3, 4, 8, 9) port total: 79 ports pull-up resistor mask rom versions total: 38 pins pd78f0828a total: 38 pins 87 chapter 4 port functions user ? s manual u16504ee1v1ud00 4.2.1 port 0 port 0 is an 4-bit input/output port with output latch. p00 to p03 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (pm0). when p00 to p03 pins are used as input pins, a pull-up resistor can be connected to them bit-wise with the pull-up resistor option register (pum). dual-function includes external interrupt request input and the external clock input for the dcan peripheral. reset input sets port 0 to input mode. figure 4-2 shows block diagram of port 0. caution: because port 0 also serves for external interrupt request input, when the port func- tion output mode is specified and the output level is changed, the interrupt request flag is set. thus, when the output mode is used, set the interrupt mask flag to 1, in order to avoid an factorized interrupt. figure 4-2: p00 to p03 configurations remarks: 1. pu0 : pull-up resistor option register 2. pm : port mode register 3. rd : port 0 read signal 4. wr : port 0 write signal p-ch wr pm wr port rd wr puo v dd p00/intp0, p01/intp1, p02/intp2, p03/cclk selector pu0 output latch (p00 to p03) pm00 to pm03 internal bus 88 chapter 4 port functions user ? s manual u16504ee1v1ud00 4.2.2 port 1 port 1 is an 5-bit input only port. dual-functions include an a/d converter analog input. figure 4-3 shows a block diagram of port 1. figure 4-3: p10 to p14 configurations remark: rd: port 1 read signal rd p10/ani0 to p14/ani4 internal bus 89 chapter 4 port functions user ? s manual u16504ee1v1ud00 4.2.3 port 2 port 2 is an 8-bit output port with output latch. p20 to p27 goes into a high impedance state when the port mode register 2 is set to 1. dual-function includes meter control pwm output. reset input sets port 2 to high-impedance state. figure 4-4 shows a block diagram of port 2. caution: when port 2 is set to 1, the read back from output latch operation is enabled. when port 2 is set to 0, the read back from output latch operation is disabled. figure 4-4: p20 to p27 configurations remarks: 1. pm : port mode register 2. rd : port 2 read signal 3. wr : port 2 write signal notes: 1. set output latch to 0 when dual function shall be applied to output. 2. disable dual function when the content of the output latch shall be applied to output. wr pm wr port rd output latch (p20 to p27) pm20 to pm27 internal bus dual function p20/sm11 to p23/sm14 note 1 note 2 p24/sm21 to p27/sm24 90 chapter 4 port functions user ? s manual u16504ee1v1ud00 4.2.4 port 3 port 3 is an 4-bit input/output port with output latch. p34 to p37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3 (pm3). when p34 to p37 are used as input pins, pull-up resistors can be connected bit-wise with the pull-up resistor option register (pu3). dual-function includes timer input/output, serial interface data input/output, serial interface clock input/output and segment signal output of the lcd controller/driver. reset input sets port 3 to input mode. figure 4-5 shows a block diagram of port 3. caution: when used as segment lines, set the port function (pf3) according to its function. figure 4-5: p34 to p37 configurations remarks: 1. pm : port mode register 2. rd : port 3 read signal 3. wr : port 3 write signal notes: 1. set output latch to 0 when dual function shall be applied to output. 2. disable dual function when the comment of the output latch shall be applied to output. wr pm wr port rd selector output latch (p34 to p37) pm34 to pm37 internal bus dual function p34/to50/ti50/s27 p35/sck3/s26 p36/so3/s25 p37/si3/s24 note 1 note 2 91 chapter 4 port functions user ? s manual u16504ee1v1ud00 4.2.5 port 4 this is an 8-bit input/output port with output latches. input mode/output mode can be specified in 1-bit units with the port mode register 4. when p40 to p47 are used as input pins, pull-up resistors can be connected bit-wise with the pull-up resistor option register (pu4). these pins are dual function pin and serve as segment signal output of lcd controller/driver. reset input sets the input mode. the port 4 block diagram is shown in figure 4-6. caution: when used as segment lines, set the port function (pf4) according to its function. figure 4-6: p40 to p47 configurations remarks: 1. puo : pull-up resistor option register 2. pm : port mode register 3. rd : port 4 read signal 4. wr : port 4 write signal notes: 1. set output latch to 0 when dual function shall be applied to output. 2. disable dual function when the comment of the output latch shall be applied to output. wr pm wr port rd p40/s7 to p47/s0 selector output latch (p40 to p47) pm40 to pm47 internal bus dual function note 1 note 2 92 chapter 4 port functions user ? s manual u16504ee1v1ud00 4.2.6 port 5 port 5 is an 8-bit output port with output latch. p50 to p57 goes into a high-impedance state when the port mode register 5 is set to 1. the dual-function includes meter control pwm output. reset input sets port 5 to high-impedance state. figure 4-7 shows a block diagram of port 5. caution: when port 5 is set to 1, the read back from output latch operation is enabled. when port 5 is set to 0, the read back from output latch operation is disabled. figure 4-7: p50 to p57 configurations remarks: 1. pm : port mode register 2. rd : port 5 read signal 3. wr : port 5 write signal notes: 1. set output latch to 0 when dual function shall be applied to output. 2. disable dual function when the comment of the output latch shall be applied to output. wr pm wr port rd p50/sm31 to p53/sm34 p54/sm41 to p57/sm44 output latch (p50 to p57) pm50 to pm57 internal bus dual function note 1 note 2 93 chapter 4 port functions user ? s manual u16504ee1v1ud00 4.2.7 port 6 port 6 is an 6-bit input/output port with output latch. p60 to p65 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (pm6). when p62 to p65 are used as input pins, pull-up resistors can be connected bit-wise with the pull-up resistor option register (pu6). the dual-function includes the asynchronous serial interface receive/transmit, the timer capture input of tm2 and the sound generator output. reset input sets port 6 to input mode. figure 4-8 shows block diagrams of port 6. figure 4-8: p60 to p65 configurations remarks: 1. pm : port mode register 2. rd : port 6 read signal 3. wr : port 6 write signal note: set output latch to 0 when dual function shall be applied to output. caution: the pull-up option is not available for p60 and p61. wr pm wr port rd p60/sgof/sgo, p61/sgoa/pcl, p62/rxd0, selector output latch p60 to p65 pm60 to pm65 internal bus p63/txd0, p64/ti20, p65/ti21 note 94 chapter 4 port functions user ? s manual u16504ee1v1ud00 4.2.8 port 8 this is a 8-bit input/output port with output latches. input mode/output mode can be specified in 1-bit units with a port mode register 8. when p80 to p87 are used as input pins, pull-up resistors can be con- nected bit-wise with the pull-up resistor option register (pu8). dual-function includes segment signal output of lcd controller/driver. reset input sets the input mode. port 8 block diagram is shown in figure 4-9. caution: when used as segment lines, set the port function pf8 according to its functions. figure 4-9: p80 to p87 configurations remarks: 1. pm : port mode register 2. rd : port 7 read signal 3. wr : port 7 write signal notes: 1. set output latch to 0 when dual function shall be applied to output. 2. disable dual function when the comment of the output latch shall be applied to output. p80/s8 p87/s15 wr pm wr port rd selector output latch (p80 to p87) pm80 to pm87 internalbus dual function note 1 note 2 95 chapter 4 port functions user ? s manual u16504ee1v1ud00 4.2.9 port 9 this is a 8-bit input/output port with output latches. input mode/output mode can be specified in 1-bit units with the port mode register 9. when p90 to p97 are used as input pins, pull-up resistors can be connected bit-wise with the pull-up resistor option register (pu9). these pins are dual function pin and serve as segment signal output of lcd controller/driver. reset input sets the input mode. the port 9 block diagram is shown in figure 4-10. caution: see port 4 with change to pf4. figure 4-10: p90 to p97 configurations remarks: 1. puo : pull-up resistor option register 2. pm : port mode register 3. rd : port 13 read signal 4. wr : port 13 write signal notes: 1. set output latch to 0 when dual function shall be applied to output. 2. disable dual function when the comment of the output latch shall be applied to output. wr pm wr port rd p90/ti22/s23, p91/to51/ti51/s22, p92/tp0/s21, p93/s20/sck31, p94/s19/so31/sio31, p95/s18/si31, p96/s17, p97/s16 selector output latch (p90 to p97) pm90 to pm97 internal bus dual function note 1 note 2 96 chapter 4 port functions user ? s manual u16504ee1v1ud00 4.3 port function control registers the following three types of registers control the ports. port mode registers (pm0, pm2 to pm6, pm8, pm9) pull-up resistor option register (pu0, pu3, pu4, pu6, pu8, pu9) port function registers (pf3, pf4, pf8, pf9) (1) port mode registers (pm0, pm2 to pm6, pm8, pm9) these registers are used to set port input/output in 1-bit units. pm0, pm2 to pm6, pm8 and pm9 are independently set with a 1-bit or 8-bit memory manipulation instruction. reset input sets registers to ffh. when port pins are used as alternate-function pins, set the port mode register and output latch according to the function. cautions: 1. pins p10 to p14 are input-only pins. 2. as port 0 has an alternate function as external interrupt request input, when the port function output mode is specified and the output level is changed, the inter- rupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. 97 chapter 4 port functions user ? s manual u16504ee1v1ud00 figure 4-11: port mode register format 76543210r/waddress after reset pm0 1 1 1 1 pm03 pm02 pm01 pm00 r/w ff20h ffh 76543210r/waddress after reset pm3 pm37 pm36 pm35 pm34 1 1 1 1 r/w ff23h ffh 76543210r/waddress after reset pm4pm47pm46pm45pm44pm43pm42pm41pm40r/wff24h ffh 76543210r/waddress after reset pm6 1 1 pm65pm64pm63pm62pm61pm60r/wff26h ffh 76543210r/waddress after reset pm8pm87pm86pm85pm84pm83pm82pm81pm80r/wff28h ffh 76543210r/waddress after reset pm9pm97pm96pm95pm94pm93pm92pm91pm90r/wff29h ffh pmmn pmmn pin input/output mode selection (m = 0, 3, 4, 6, 8, 9; n = 0 - 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 76543210r/waddress after reset pm2pm27pm26pm25pm24pm23pm22pm21pm20r/wff22h ffh 76543210r/waddress after reset pm5pm57pm56pm55pm54pm53pm52pm51pm50r/wff25h ffh pmmn pmmn pin output buffer selection (m = 2, 5; n = 0 - 7) 0 output mode (output buffer on) 1 hi-z mode (output buffer off) 98 chapter 4 port functions user ? s manual u16504ee1v1ud00 (2) pull-up resistor option register (pu0, pu3, pu4, pu6, pu8, pu9) this register is used to set whether to use an internal pull-up resistor at each port or not. a pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with pum (m = 0, 3, 4, 6, 8, 9). no on-chip pull-up resistors can be used to the bits set to the output mode, irrespective of pu setting. pum is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 4-12: pull-up resistor option register (pum) format remark: the pull-up option is not available for p60 and p61. caution: once the software can't use pull-up resistors are connected by setting 1 to the pull-up resistor option register, they are not disconnected even in output mode. to switch off the pull-up resistors must be written to the pull-up resistor option register. 76543210r/waddress after reset pu00000pu03pu02pu01pu00r/wff30h00h 76543210r/waddress after reset pu3pu37pu36pu35pu340000r/wff33h00h 76543210r/waddress after reset pu4 pu47 pu46 pu45 pu44 pu43 pu42 pu41 pu40 r/w ff34h 00h 76543210r/waddress after reset pu6 0 0 pf65 pf64 pf63 pf62 0 0 r/w ff36h 00h 76543210r/waddress after reset pu8 pu87 pu86 pu85 pu84 pu83 pu82 pu81 pu80 r/w ff38h 00h 76543210r/waddress after reset pu9 pu97 pu96 pu95 pu94 pu93 pu92 pu91 pu90 r/w ff39h 00h pumn pumn pin internal pull-up resistor selection (m = 0, 3, 4, 6, 8, 9; n = 0 - 7) 0 on-chip pull-up resistor not used 1 on-chip pull-up resistor used 99 chapter 4 port functions user ? s manual u16504ee1v1ud00 (3) port function register (pf3, pf4, pf8 and pf9) this register is used to set the lcd segment function of ports 3, 4, 8 and 9. pf3, pf8 and pf9 are set with an 1-bit or 8-bit manipulation instruction. pf4 is set with an 8-bit manipulation instruction. reset input sets this register to 00h. figure 4-13: port function register (pf3, pf4, pf8 and pf9) format caution: for pf4 it is only allowed to set 00h or ffh. for pf3 only the 4 msb are relevant. 76543210r/waddress after reset pf3 pf37 pf36 pf35 pf34 0 0 0 0 r/w ff53h 00h 76543210r/waddress after reset pf4 pf47 pf46 pf45 pf44 pf43 pf42 pf41 pf40 r/w ff54h 00h 76543210r/waddress after reset pf8 pf87 pf86 pf85 pf84 pf83 pf82 pf81 pf80 r/w ff58h 00h 76543210r/waddress after reset pf9 pf97 pf96 pf95 pf94 pf93 pf92 pf91 pf90 r/w ff59h 00h pfmn pfmn port function selection (m = 3, 4, 8, 9; n = 0 - 7) 0 port function 1 lcd segment function 100 chapter 4 port functions user ? s manual u16504ee1v1ud00 4.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 writing to input/output port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution: in the case of 1-bit memory manipulation instruction, although a single bit is manipu- lated the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit. 4.4.2 reading from input/output port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 101 chapter 4 port functions user ? s manual u16504ee1v1ud00 4.4.3 operations on input/output port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution: in the case of 1-bit memory manipulation instruction, although a single bit is manipu- lated the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 102 user ? s manual u16504ee1v1ud00 [memo] 103 user ? s manual u16504ee1v1ud00 chapter 5 clock generator 5.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following type of system clock oscillators is available. (1) main system clock oscillator this circuit oscillates at frequencies of 4 to 8.38 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register. 5.2 clock generator configuration the clock generator consists of the following hardware. figure 5-1: block diagram of clock generator note: the standby function is described in the chapter 21 ? standby function ? on page 373". table 5-1: clock generator configuration item configuration control register processor clock control register (pcc) oscillator main system clock oscillator subsystem clock oscillator f x f x f x 2 f x 3 2 f x 4 2 cpu clock (f prescaler selector 22 prescaler clock to peripheral hardware main system clock oscillator f x stop x1 x2 standby control circuit note cpu ) 104 chapter 5 clock generator user ? s manual u16504ee1v1ud00 5.3 clock generator control register the clock generator is controlled by the processor clock control register (pcc). (1) processor clock control register (pcc) the pcc selects a cpu clock and the division ratio at the cpu clock. the pcc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets the pcc to 04h. figure 5-2: processor clock control register format caution: bit 3 to bit 7 must be set to 0. remark: f x : main system clock oscillation frequency 76543210r/waddress after reset pcc00000pcc2pcc1pcc0r/wfffbh04h pcc2 pcc1 pcc0 cpu clock selection (f cpu ) 000 f x 001 f x /2 010 f x /2 2 011 f x /2 3 100 f x /2 4 other than above setting prohibited 105 chapter 5 clock generator user ? s manual u16504ee1v1ud00 5.4 system clock oscillator 5.4.1 main system clock oscillator the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 8.0 mhz) connected to the x1 and x2 pins. external clocks can be input to the main system clock oscillator. in this case, the clock signal is supplied to the x1 pin and the x2 pin has to be left open. figure 5-3 shows an external circuit of the main system clock oscillator. figure 5-3: external circuit of main system clock oscillator (a) crystal and ceramic oscillation (b) external clock caution: do not execute the stop instruction if an external clock is input. this is because when the stop instruction is used the main system clock operation stops and the x2 pin is connected to v dd1 via a pull-up resistor. x2 x1 ic crystal or ceramic resonator external clock x2 x1 open pd74hcu04 106 chapter 5 clock generator user ? s manual u16504ee1v1ud00 figure 5-4: examples of oscillator with bad connection (1/3) (a) wiring of connection circuits is too long (b) a signal line crosses over oscillation circuit lines ic x2 x1 x2 x1 portn (n = 0 to 10, 12, 13) ic 107 chapter 5 clock generator user ? s manual u16504ee1v1ud00 figure 5-4: examples of oscillator with bad connection (2/3) (c) changing high current is too near a signal conductor (d) current flows through the grounding line of the oscillator (potential at points a, b, and c fluctuate) ic x2 x1 high current ic x2 ab c pnm v dd high current x1 108 chapter 5 clock generator user ? s manual u16504ee1v1ud00 figure 5-4: examples of oscillator with bad connection (3/3) (e) signals are fetched ic x2 x1 109 chapter 5 clock generator user ? s manual u16504ee1v1ud00 5.5 clock generator operations the clock generator generates the following various types of clocks and controls the cpu operating mode including the standby mode. main system clock f x cpu clock f cpu clock to peripheral hardware the following clock generator functions and operations are determined with the processor clock control register (pcc). (a) upon generation of reset signal, the lowest speed mode of the main system clock (4 s when operated at 8.0 mhz) is selected (pcc = 04h). main system clock oscillation stops while low level is applied to reset pin. (b) with the main system clock selected, one of the five cpu clock stages (f x , f x /2, f x /2 2 , f x /2 3 or f x /2 4 ) can be selected by setting the pcc. (c) with the main system clock selected, two standby modes, the stop and halt modes, are available. 110 chapter 5 clock generator user ? s manual u16504ee1v1ud00 5.6 changing system clock and cpu clock settings 5.6.1 time required for switchover between system clock and cpu clock the system clock and cpu clock can be switched over by means of bit 0 to bit 2 (pcc0 to pcc2) of the processor clock control register (pcc). the actual switchover operation is not performed directly after writing to the pcc, but operation contin- ues on the pre-switchover clock for several instructions (see table 5-2). table 5-2: maximum time required for cpu clock switchover set values after switchover set values before switchover pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 000001010011100 0 0 0 8 instructions 4 instructions 2 instructions 1 instruction 0 0 1 16 instructions 4 instructions 2 instructions 1 instruction 0 1 0 16 instructions 8 instructions 2 instructions 1 instruction 0 1 1 16 instructions 8 instructions 4 instructions 1 instruction 1 0 0 16 instructions 8 instructions 4 instructions 2 instructions 111 chapter 5 clock generator user ? s manual u16504ee1v1ud00 5.6.2 system clock and cpu clock switching procedure this section describes switching procedure between system clock and cpu clock. figure 5-5: system clock and cpu clock switching (1) the cpu is reset by setting the reset signal to low level after power-on. after that, when reset is released by setting the reset signal to high level, main system clock starts oscillation. at this time, oscillation stabilization time (2 17 /f x ) is secured automatically. after that, the cpu starts executing the instruction at the minimum speed of the main system clock (4 s when operated at 8.0 mhz). (2) after the lapse of a sufficient time for the v dd voltage to increase to enable operation at maximum speeds, the processor clock control register (pcc) is rewritten and the maximum-speed operation is carried out. v dd reset interrupt request signal system clock cpu clock wait (16.3 ms: 8.0 mhz) internal reset operation minimum speed operation maximum operation f x f x speed 112 user ? s manual u16504ee1v1ud00 [memo] 113 user ? s manual u16504ee1v1ud00 chapter 6 16-bit timer 2 6.1 16-bit timer 2 functions the 16-bit timer 2 (tm2) has the following functions. pulse width measurement divided output of input pulse time stamp function for the dcan figure 6-1 shows 16-bit timer 2 block diagram. figure 6-1: timer 2 (tm2) block diagram (1) pulse width measurement tm2 can measure the pulse width of an external input signal. (2) divided output of input pulse the frequency of an input signal can be divided and the divided signal can be output. (3) timer stamp function for the dcan an internal signal output of the dcan-module can be used to build a time stamp function of the system (please refer to the chapter of the dcan-module). internal bus internal bus 16-bit timer register (tm2) 16-bit capture register (cr22) edge detection circuit es01, es00 tpoe es11, es10 es21, es20 16-bit capture register (cr21) 16-bit capture register (cr20) intovf inttm22 inttm21 inttm20 es21 es20 es11 fx/4 fx/8 fx/32 fx/128 es10 es01 crc21 tmc22 tpoe crc20 es00 prm21prm20 prescaler mode register (prm2) capture pulse control register (crc2) 16-bit timer mode control register (tmc2) selector ti22/s23/p90 ti21/p65 ti20/p64 tpo/s21/p92 prescaler 1, ? , ? , 1/8 noise rejection circuit noise rejection circuit noise rejection circuit edge detection circuit edge detection circuit dcan 114 chapter 6 16-bit timer 2 user ? s manual u16504ee1v1ud00 6.2 16-bit timer 2 configuration timer 2 consists of the following hardware. (1) 16-bit timer register (tm2) tm2 is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of an input clock. the count value is reset to 0000h in the following case: at reset input the count value is undefined in the following case: - tmc22 is disabled. caution: when the timer tm2 is disabled, the value of the timer register tm2 will be undefined. (2) capture register 20 (cr20) the valid edge of the ti20 pin can be selected as the capture trigger. setting of the ti20 valid edge is performed by setting of the prescaler mode register (prm2). when the valid edge of the ti20 is detected, an interrupt request (inttm20) is generated. cr20 is read by a 16-bit memory manipulation instruction. after reset input, the value of cr20 is undefined. table 6-1: timer 2 configuration item configuration timer register 16 bits x 1 (tm2) register capture register: 16 bits 115 chapter 6 16-bit timer 2 user ? s manual u16504ee1v1ud00 (3) capture register 21 (cr21) the valid edge of the ti21 pin can be selected as the capture trigger. setting of the ti21 valid edge is performed by setting of the prescaler mode register (prm2). when the valid edge of the ti21 is detected, an interrupt request (inttm21) is generated. cr21 is read by a 16-bit memory manipulation instruction. after reset input, the value of cr21 is undefined. (4) capture register 22 (cr22) the valid edge of the ti22 pin can be selected as the capture trigger. setting of the ti22 valid edge is performed by setting of the prescaler mode register (prm2). when the valid edge of the ti22 is detected, an interrupt request (inttm22) is generated. cr22 is read by a 16-bit memory manipulation instruction. after reset input, the value of cr22 is undefined. 116 chapter 6 16-bit timer 2 user ? s manual u16504ee1v1ud00 6.3 16-bit timer 2 control registers the following three types of registers are used to control timer 0. 16-bit timer mode control register (tmc2) capture pulse control register (crc2) prescaler mode register (prm2) (1) 16-bit timer mode control register (tmc2) this register sets the 16-bit timer operating mode and controls the prescaler output signals. tmc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc2 value to 00h. figure 6-2: 16-bit timer mode control register (tmc2) format cautions: 1. before changing the operation mode, stop the timer operation (by setting 0 to tmc22). 2. bit 1 and bits 3 to 7 must be set to 0. 76543<2>1<0>r/waddress after reset tmc200000tmc220tpoer/wff65h00h tmc2 timer 2 operating mode selection 0 operation stop 1 operation enabled tpoe timer 2 prescaler output control 0 prescaler signal output disabled 1 prescaler signal output enabled 117 chapter 6 16-bit timer 2 user ? s manual u16504ee1v1ud00 (2) capture pulse control register (crc2) this register specifies the division ratio of the capture pulse input to the 16-bit capture register (cr22) from an external source. crc2 is set with an 8-bit memory manipulation instruction. reset input sets crc2 value to 00h. figure 6-3: capture pulse control register (crc2) format cautions: 1. timer operation must be stopped before setting crc2. 2. bits 2 to 7 must be set to 0. 76543210r/waddress after reset crc2000000crc21 crc20 r/w ff67h 00h crc21 crc20 ti22 - capture pulse selection 0 0 does not divide capture pulse (ti22) 0 1 divides capture pulse by 2 (ti22/2) 1 0 divides capture pulse by 4 (ti22/4) 1 1 divides capture pulse by 8 (ti22/8) 118 chapter 6 16-bit timer 2 user ? s manual u16504ee1v1ud00 (3) prescaler mode register (prm2) this register is used to set 16-bit timer (tm2) count clock and valid edge of ti2n (n = 0 to 2) input. prm2 is set with an 8-bit memory manipulation instruction. reset input sets prm2 value to 00h. figure 6-4: prescaler mode register (prm2) format caution: timer operation must be stopped before setting prm2. 76543210r/waddress after reset prm2 es21 es20 es11 es10 es01 es00 prm21 prm20 r/w ff66h 00h es21 es20 ti02 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es11 es10 ti01 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es01 es00 ti00 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm21 prm20 count clock selection 00 f x /2 3 01 f x /2 4 10 f x /2 5 11 f x /2 6 119 chapter 6 16-bit timer 2 user ? s manual u16504ee1v1ud00 6.4 16-bit timer 2 operations 6.4.1 pulse width measurement operations it is possible to measure the pulse width of the signals input to the timer input pins by using the 16-bit timer register (tm2). tm2 is used in free-running mode. (1) pulse width measurement with free-running counter and one capture register (ti20) when the edge specified by the prescaler mode register (prm2) is input to the ti20 pin, the value of tm2 is taken into 16-bit capture register 20 (cr20) and an external interrupt request signal (inttm20) is set. any of three edge specifications can be selected - rising, falling, or both edges - by means of bits 2 and 3 (es00 and es01) of prm2. for valid edge detection, sampling is performed at the count clock selected by prm2, and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 6-5: configuration diagram for pulse width measurement by using the free running counter fx/2 3 fx/2 4 fx/2 5 fx/2 6 ti20 16-bit timer register (tm2) intovf 16-bit capture register 20 (cr20) internal bus inttm20 selector 120 chapter 6 16-bit timer 2 user ? s manual u16504ee1v1ud00 figure 6-6: timing of pulse width measurement operation by using the free running counter and one capture register (with both edges specified) t count clock tm0 count value value loaded to cr00 intovf 0000h 0001h d0 d1 ffffh 0000h d2 d3 d3 d2 d1 d0 (d1 ? d0) x t (10000h ? d1 + d2) x t (d3 ? d2) x t ti00 pin input inttm00 121 chapter 6 16-bit timer 2 user ? s manual u16504ee1v1ud00 (2) measurement of three pulse widths with the free running counter the 16-bit timer register (tm2) allows simultaneous measurement of the pulse widths of the three signals input to the ti20 to ti22 pins. when the edge specified by bits 2 and 3 (es00 and es01) of prescaler mode register (prm2) is input to the ti20 pin, the value of tm2 is taken into 16-bit capture register 20 (cr20) and an exter- nal interrupt request signal (inttm20) is set. also, when the edge specified by bits 4 and 5 (es10 and es11) of prm0 is input to the ti21 pin, the value of tm2 is taken into 16-bit capture register 21 (cr21) and an external interrupt request signal (inttm21) is set. when the edge specified by bits 6 and 7 (es20 and es21) of prm2 is input to the ti22 pin, the value of tm2 is taken into 16-bit capture register 22 (cr22) and external interrupt request signal (inttm22) is set. any of three edge specifications can be selected - rising, falling, or both edges - as the valid edges for the ti20 to ti22 pins by means of bits 2 and 3 (es00 and es01), bits 4 and 5 (es10 and es11), and bits 6 and 7 (es06 and es07) of prm2, respectively. for ti20 pin valid edge detection, sampling is performed at the interval selected by the prescaler mode register (prm2), and a capture operation is only performed when a valid level is detected twice, thus eliminates the noise of a short pulse width. capture operation capture register operation in capture trigger input is shown. figure 6-7: cr2m capture operation with rising edge specified remark: m = 0 to 2 count clock tm2 ti2m rising edge detection cr2m inttm2m n ? 3n ? 2n ? 1 n n+1 n 122 chapter 6 16-bit timer 2 user ? s manual u16504ee1v1ud00 figure 6-8: timing of pulse width measurement operation by free running counter (with both edges specified) remark: m = 0 to 2, n = 1, 2 count clock tm2 count value ti2m pin input value loaded to cr2m inttm2m ti2n pin input value loaded to cr2n inttm2n intovf (d1 ? d0) x t (10000h ? d0 + d2) x t (10000h ? d1 + (d2 + 1) x t (d3 ? d2) x t t 0000h 0001h d0 d1 ffffh 0000h d2 d3 d3 d1 d0 d1 d2 123 chapter 6 16-bit timer 2 user ? s manual u16504ee1v1ud00 6.5 16-bit timer 2 precautions (1) timer start errors an error with a maximum of one clock may occur until counting is started after timer start, because the 16-bit timer register (tm2) can be started asynchronously with the count pulse. figure 6-9: 16-bit timer register start timing (2) capture register data retention timings if the valid edge of the ti2n pin is input during the 16-bit capture register 0m (cr2n) is read, cr2m performs capture operation, but the capture value is not guaranteed. however, the interrupt request flag (inttm2n) is set upon detection of the valid edge. figure 6-10: capture register data retention timing remark: n = 0 to 2 tm2 count value 0000h 0001h 0002h 0004h count pulse timer start 0003h count pulse tm2 count value edge input interrupt request flag capture read signal cr0n interrupt value n-3 n-2 n-1 n n+1 m-3 m-2 m-1 m m+1 m+2 m+3 x n capture operation n 124 chapter 6 16-bit timer 2 user ? s manual u16504ee1v1ud00 (3) valid edge setting set the valid edge of the ti2m/p3m pin after setting bit 2 (tmc22) of the 16-bit timer mode control register to 0, and then stopping timer operation. valid edge setting is carried out with bits 2 to 7 (esm0 and esm1) of the prescaler mode register (prm2). remark: m = 0 to 2 (4) occurrence of inttm2n inttm2n occurs even if no capture pulse exists, immediately after the timer operation has been started (tmc02 of tmc2 has been set to 1) with a high level applied to the input pins ti20 to ti22 of 16-bit timer 2. this occurs if the rising edge (with esn1 and esn0 of prm0 set to 0, 1), or both the rising and falling edges (with esn1 and esn0 of prm2 set to 1, 1) are selected. inttm2n does not occur if a low level is applied to ti20 to ti22. (5) timer stop when the timer tm2 is disabled, the value of the timer register will be undefined. 125 user ? s manual u16504ee1v1ud00 chapter 7 8-bit timer/event counters 50 and 51 7.1 8-bit timer/event counters 50 and 51 functions the timer 50 and 51 have the following two modes: mode using tm50 and tm51 alone (individual mode) mode using the cascade connection (16-bit cascade mode connection). (1) mode using tm50 and tm51 as 8-bit timers the timer operate as 8-bit timer/event counters. they have the following functions: interval timer external event counter square-wave output pwm output (2) mode using the cascade connection as 16-bit timer the timer operates as 16-bit timer/event counter. it has the following functions: interval timer external event counter square-wave output 126 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 7.1.1 8-bit operation modes (1) 8-bit interval timer interrupts are generated at the present time intervals. remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. table 7-1: 8-bit timer/event counter 50 interval times minimum interval width maximum interval width resolution 2 3 table 7-2: 8-bit timer/event counter 51 interval times minimum interval width maximum interval width resolution 2 4 127 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 (2) external event counter the number of pulses of an externally input signal can be measured. (3) square-wave output a square wave with any selected frequency can be output. remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. (4) pwm output tm50 and tm51 can generate an 8-bit resolution pwm output. table 7-3: 8-bit timer/event counter 50 square-wave output ranges minimum interval width maximum interval width resolution 2 3 table 7-4: 8-bit timer/event counter 51 square-wave output ranges minimum interval width maximum interval width resolution 2 4 128 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 7.1.2 16-bit operation modes (1) interval timer interrupts are generated at the present interval time. (2) external event counter the number of pulses of an externally input signal can be measured. (3) square-wave output a square wave with any selected frequency can be output. remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. table 7-5: 16-bit timer/event counter tm50/tm51 interval times minimum interval width maximum interval width resolution 2 3 table 7-6: 16-bit timer/event counter tm50/tm51 square-wave output ranges minimum interval width maximum interval width resolution 2 3 129 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 7.2 8-bit timer/event counters 50 and 51 configurations the 8-bit timer/event counters 50 and 51 consist of the following hardware. figure 7-1: 8-bit timer/event counter 50 block diagram note: refer to figure 7-2 for details of configurations of 8-bit timer/event counters 50 and 51 output control circuits. table 7-7: 8-bit timer/event counters 50 and 51 configurations item configuration timer register 8 bits x 2 (tm50, tm51) register compare register 8 bits x 2 (cr50, cr51) timer output 2 (to50, to51) control register timer clock select register 50 and 51 (tcl50, tcl51) 8-bit timer mode control registers 50 and 51 (tmc50, tmc51) port mode registers 3 and 9 (pm3, pm9) internal bus internal bus ti50/p34/s27 f x /2 3 f x /2 5 f x /2 7 f x /2 8 f x /2 9 f x /2 11 selector 8-bit compare register 50 (cr50) match 8-bit counter 50 (tm50) 3 selector mask circuit clear ovf tcl502 tcl501 tcl500 timer clock select register 50 (tcl50) timer mode control register 50 (tmc50) tce50 tmc506 lvs50 lvr50 tmc501 toe50 s r inv s q r selector inttm50 selector tio50/p34/s27 level inversion 130 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 figure 7-2: 8-bit timer/event counter 51 block diagram note: refer to figure 7-3 for details of configurations of 8-bit timer/event counters 50 and 51 output control circuits. figure 7-3: block diagram of 8-bit timer/event counters 50 and 51 output control circuit remarks: 1. the section in the broken line is an output control circuit. 2. n = 50, 51 internal bus internal bus selector 8-bit compare register 51 (cr51) match 8-bit counter 51 (tm51) 3 selector mask circuit clear ovf tcl512 tcl511 tcl510 timer clock select register 51 (tcl51) timer mode control register 51 (tmc51) tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 s r inv s q r selector inttm51 selector tio51/p91/s22 level inversion ti51/p91/s22 f x /2 4 f x /2 6 f x /2 7 f x /2 8 f x /2 10 f x /2 12 reset lvrn lvsn tmcn1 tmcn6 ovfn inttmn tcen inttmn r s q pwm output circuit timer output f/f2 level f/f r s inv q tmcn1 tmcn6 selector p34, p91 output latch pm34, pm91 to50/p34/s27/ti50, to51/p91/s22/ti51 toen 131 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 (1) compare register 50 and 51 (cr50, 51) these 8-bit registers compare the value set to cr50 to 8-bit timer register 5 (tm50) count value, and the value set to cr51 to the 8-bit timer register 51 (tm51) count value, and, if they match, generate interrupts request (inttm50 and inttm51, respectively). cr50 and cr51 are set with an 8-bit memory manipulation instruction. they cannot be set with a 16-bit memory manipulation instruction. the 00h to ffh values can be set. reset input sets cr50 and cr51 values to 00h. cautions: 1. to use pwm mode, set crn value before setting tmcn (n = 50, 51) to pwm mode. 2. if the data is set in cascade mode, always set it after stopping the timer. (2) 8-bit timer registers 50 and 51 (tm50, tm51) these 8-bit registers count pulses. tm50 and tm51 are read with an 8-bit memory manipulation instruction. reset input sets tm50 and tm51 to 00h. caution: the cascade connection time becomes 00h even when the bit tce50 of the timer tm50 is cleared. 132 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 7.3 8-bit timer/event counters 50 and 51 control registers the following three types of registers are used to control the 8-bit timer/event counters 50 and 51. timer clock select register 50 and 51 (tcl50, tcl51) 8-bit timer mode control registers 50 and 51 (tmc50, tmc51) port mode register 0 (pm3, pm9) (1) timer clock select register 50 (tcl50) this register sets count clocks of 8-bit timer register 50. tcl50 is set with an 8-bit memory manipulation instruction. reset input sets tcl50 to 00h. figure 7-4: timer clock select register 50 format note: when clock is input from the external, timer output (pwm output) cannot be used. cautions: 1. when rewriting tcl50 to other data, stop the timer operation beforehand. 2. set always bits 3 to 7 to "0". remarks: 1. f x : main system clock oscillation frequency 2. ti50: 8-bit timer register 50 input pin 3. values in parentheses apply to operation with f x = 8.0 mhz 76543210r/waddress after reset tcl5000000tcl502tcl501tcl500r/wff71h00h tcl502 tcl501 tcl500 8-bit timer register 50 count clock selection 000 ti50 falling edge note 001 ti50 rising edge note 010 f x /2 3 (1.0 mhz) 011 f x /2 5 (250 khz) 100 f x /2 7 (62.5 khz) 101 f x /2 8 (31.25 khz) 110 f x /2 9 (15.6 khz) 111 f x /2 11 (3.9 khz) other than above setting prohibited 133 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 (2) timer clock select register 51 (tcl51) this register sets count clocks of 8-bit timer register 51. tcl51 is set with an 8-bit memory manipulation instruction. reset input sets tcl51 to 00h. figure 7-5: timer clock select register 51 format note: when clock is input from the external, timer output (pwm output) cannot be used. cautions: 1. when rewriting tcl51 to other data, stop the timer operation beforehand. 2. set always bits 3 to 7 to "0". remarks: 1. f x : main system clock oscillation frequency 2. ti51: 8-bit timer register 51 input pin 3. values in parentheses apply to operation with f x = 8.0 mhz 76543210r/waddress after reset tcl5100000tcl512tcl511tcl510r/wff75h00h tcl512 tcl511 tcl510 8-bit timer register 51 count clock selection 000 ti51 falling edge note 001 ti51 rising edge note 010 f x /2 4 (500 khz) 011 f x /2 6 (125 khz) 100 f x /2 7 (62.5 khz) 101 f x /2 8 (31.25 khz) 110 f x /2 10 (7.8 khz) 111 f x /2 12 (1.9 khz) other than above setting prohibited 134 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 (3) 8-bit timer mode control register 50 (tmc50) this register enables/stops operation of 8-bit timer register 50, sets the operating mode of 8-bit timer register 50 and controls operation of 8-bit timer/event counter 50 output control circuit. it selects the r-s flip-flop (timer output f/f 1, 2) setting/resetting, the active level in pwm mode, inversion enabling/disabling in modes other than pwm mode and 8-bit timer/event counter 5 timer output enabling/disabling. tmc50 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc50 to 00h. figure 7-6: 8-bit timer mode control register 50 format cautions: 1. timer operation must be stopped before setting tmc50. 2. if lvs50 and lvr50 are read after data are set, they will be 0. 3. be sure to set bit 4 and bit 5 to 0. <7> 6 5 4 <3> <2> 1 <0> r/w address after reset tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 r/w ff70h 00h toe50 8-bit timer/event counter 50 output control 0 output disabled (port mode) 1 output enabled tmc501 in pwm mode in other mode active level selection timer output f/f1 control 0 active high inversion operation disabled 1 active low inversion operation enabled lvs50 lvr50 8-bit timer/event counter 50 timer output f/f1 status setting 0 0 no change 0 1 timer output f/f1 reset (0) 1 0 timer output f/f1 set (1) 1 1 setting prohibited tmc506 8-bit timer/event counter 50 operating mode selection 0 clear & start mode on match of tm50 and cr50 1 pwm mode (free-running) tce50 8-bit timer register 50 operation control 0 operation stop (tm50 clear to 0) 1 operation enable 135 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 (4) 8-bit timer mode control register 51 (tmc51) this register enables/stops operation of 8-bit timer register 51, sets the operating mode of 8-bit timer register 51 and controls operation of 8-bit timer/event counter 51 output control circuit. it selects the r-s flip-flop (timer output f/f 1, 2) setting/resetting, active level in pwm mode, inver- sion enabling/disabling in modes other than pwm mode and 8-bit timer/event counter 51 timer output enabling/disabling. tmc51 is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets tmc51 to 00h. figure 7-7: 8-bit timer mode control register 51 format (1/2) <7> 6 5 4 <3> <2> 1 <0> r/w address after reset tmc51 tce51 tmc516 0 tmc514 lvs51 lvr51 tmc511 toe51 r/w ff74h 00h toe51 8-bit timer/event counter 51 output control 0 output disabled (port mode) 1 output enabled tmc511 in pwm mode in other mode active level selection timer output f/f1 control 0 active high inversion operation disabled 1 active low inversion operation enabled lvs51 lvr50 8-bit timer/event counter 51 timer output f/f1 status setting 0 0 no change 0 1 timer output f/f1 reset (0) 1 0 timer output f/f1 set (1) 1 1 setting prohibited tmc514 individual of cascade mode connection 0 individual mode (8-bit timer/counter mode) 1 cascade connection mode (16-bit timer/counter mode) 136 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 figure 7-7: 8-bit timer mode control register 51 format (2/2) cautions: 1. timer operation must be stopped before setting tmc51. 2. if lvs51 and lvr51 are read after data are set, they will be 0. 3. be sure to set bit 5 to 0. (5) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p34/ti50/to50/s27 pin for timer output, set pm34 and the output latch of p34 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 7-8: port mode register 3 format tmc516 8-bit timer/event counter 51 operating mode selection 0 clear & start mode on match of tm51 and cr51 1 pwm mode (free-running) tce51 8-bit timer register 51 operation control 0 operation stop (tm51 clear to 0) 1 operation enable 76543210r/waddress after reset pm3 pm37 pm36 pm35 pm34 1 1 1 1 r/w ff23h ffh pm3n pm3n input/output mode selection (n = 4 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 137 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 (6) port mode register 9 (pm9) this register sets port 9 input/output in 1-bit units. when using the p91/ti51/to51/s22 pin for timer output, set pm91 and the output latch of p91 to 0. pm9 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm9 to ffh. figure 7-9: port mode register 9 format 76543210r/waddress after reset pm9pm97pm96pm95pm94pm93pm92pm91pm90r/wff29h ffh pm9n pm9n input/output mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 138 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 7.4 8-bit timer/event counters 50 and 51 operations 7.4.1 interval timer operations setting the 8-bit timer mode control registers (tmc50 and tmc51) as shown in figure 8-9 allows oper- ation as an interval timer. interrupts are generated repeatedly using the count value preset in 8-bit com- pare registers (cr50 and cr51) as the interval. when the count value of the 8-bit timer register 50 or 51 (tm50, tm51) matches the value set to cr50 or cr51, counting continues with the tm50 or tm51 value cleared to 0 and the interrupt request signal (inttm50, inttm51) is generated. count clock of the 8-bit timer register 50 (tm50) can be selected with the timer clock select register 50 (tcl50) and count clock of the 8 bit timer register 51 (tm51) can be selected with the timer clock select register 51 (tcl51). figure 7-10: 8-bit timer mode control register settings for interval timer operation setting method (1) set each register tcl5n : selects the count clock cr5n : compare value tmc5n : selects the clear and start mode when tm5n and cr5n match. (tmc5n = 0000xxxx0b, x is not done care). (2) when tce5n = 1 is set, counting starts. (3) when the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). (4) then, inttm5n is repeatedly generated during the same interval. when counting stops, set tce5n = 0. remarks: 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. 2. n = 50, 51 3. tmc5n4 is only available at tm51. 1 tcen 0 tmcn6 0 0 0/1 lvsn lvrn tmcn1 toen tmcn 0/1 0/1 0/1 clear and start on match of tmn and crn tmn operation enable tm5n cascadation mode tmcn4 139 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 figure 7-11: interval timer operation timings (1/3) (a) when n = 00h to ffh remarks: 1. interval time = (n + 1) x t: n = 00h to ffh 2. n = 50, 51 (b) when crn = 00h remark: n = 50, 51 t 00 01 n 00 01 n 00 01 n n n n n clear clear count start interrupt acknowledge interrupt acknowledge interval time interval time interval time count clock tmn count value crn tcen inttmn ton t count clock tmn crn tcen inttmn tion interval time 00h 00h 00h 00h 00h 140 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 figure 7-11: interval timer operation timings (2/3) (c) when crn = ffh remark: n = 50, 51 (d) operated by cr5n transition (m < n) remark: n = 50, 51 t count clock tmn crn tcen inttmn tion 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt received interrupt received count clock tmn crn tcen inttmn tion 00h n n m n ffh 00h m 00h m crn transition tmn overflows since m < n 141 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 figure 7-11: interval timer operation timings (3/3) (e) operated by cr5n transition (m > n) remark: n = 50, 51 count clock tmn crn tcen inttmn tion n < < 142 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operation with f x = 8.0 mhz. table 7-8: 8-bit timer/event counters 50 interval times tcln2 tcln1 tcln0 minimum interval time maximum interval time resolution 0 0 0 t/n input cycle 2 8 table 7-9: 8-bit timer/event counters 51 interval times tcln2 tcln1 tcln0 minimum interval time maximum interval time resolution 0 0 0 t/n input cycle 2 8 143 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 7.4.2 external event counter operation the external event counter counts the number of external clock pulses to be input to the ti50/p34/522/to50 and ti51/521/522/to51 pins with 8-bit timer registers 50 and 51 (tm50 and tm51). tm50 and tm51 are incremented each time the valid edge specified with timer clock select registers 50 and 51 (tcl50 and tcl51) is input. either rising or falling edge can be selected. when the tm50 and tm51 counted values match the values of 8-bit compare registers (cr50 and cr51), tm50 and tm51 are cleared to 0 and the interrupt request signals (inttm50 and inttm51) are generated. figure 7-12: 8-bit timer mode control register setting for external event counter operation remarks: 1. n = 50, 51 2. x: don ? t care figure 7-13: external event counter operation timings (with rising edge specified) remarks: 1. n = 00h to ffh 2. n = 50, 51 1 tcen 0 tmcn6 00x lvsn lvrn tmcn1 toen tmcn xx0 ton output disable clear & start mode on match of tmn and crn tmn operation enable tmcn4 00 01 13 n count clock tmn count value crn tcen inttmn 05 n-1 00 02 03 01 02 04 n 144 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 7.4.3 square-wave output a square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers (cr50 and cr51). the to50/p34/527/ti50 or to51/p91/522/ti51 pin output status is reversed at intervals of the count value preset to cr50 or cr51 by setting bit 1 (tmc501) and bit 0 (toe50) of the 8-bit timer output control register 5 (tmc50), or bit 1 (tmc511) and bit 0 (toe51) of the 8-bit timer mode control register 6 (tmc51) to 1. this enables a square wave of a selected frequency to be output. figure 7-14: 8-bit timer mode control register settings for square-wave output operation setting method (1) set the registers set the port latch and port mode register to 0. tcl5n : selects the count clock cr5n : compare value tmc5n : selects the clear and start mode when tm5n and cr5n match. inversion of timer output flip-flop enabled timer output enabled 145 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 figure 7-15: square-wave output operation timing note: ton output initial value can be set by bits 2 and 3 (lvrn, lvsn) of the 8-bit timer mode control register tcmn. remark: n = 50, 51 remarks: 1. main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. 3. n = 50, 51 table 7-10: 8-bit timer/event counters 50 square-wave output ranges minimum pulse time maximum pulse time resolution 2 3 table 7-11: 8-bit timer/event counters 51 square-wave output ranges minimum pulse time maximum pulse time resolution 2 4 146 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 7.4.4 pwm output operations setting the 8-bit timer mode control registers (tmc50 and tmc51) as shown in figure 8-14 allows operation as pwm output. pulses with the duty rate determined by the values preset in 8-bit compare registers (cr50 and cr51) output from the to50/p34/527/ti50 or to51/p91/522/ti51 pin. select the active level of pwm pulse with bit 1 of the 8-bit timer mode control register 50 (tmc50) or bit 1 of the 8-bit timer mode control register 51 (tmc51). this pwm pulse has an 8-bit resolution. the pulse can be converted into an analog voltage by integrat- ing it with an external low-pass filter (lpf). count clock of the 8-bit timer register 50 (tm50) can be selected with the timer clock select register 50 (tcl50) and count clock of the 8-bit timer register 51 (tm51) can be selected with the timer clock select register 51 (tcl51). pwm output enable/disable can be selected with bit 0 (toe50) of tmc50 or bit 0 (toe51) of tmc51. figure 7-16: 8-bit timer control register settings for pwm output operation setting method (1) set the port latch and port mode register to "0". (2) set the active level width in the 8-bit compare register n (cr5n). (3) select the count clock in the timer clock selection register n (tcl5n). (4) set the active level in bit 1 (tmc5n1) of tmc5n. (5) if bit 7 (tce5n) of tmc5n is set to "1", counting starts. when counting starts, set tce5n to "0". remarks: 1. n = 50, 51 2. x: don ? t care pwm output operation (1) when counting starts, the pwm output (output from to5n) outputs the inactive level until an overflow occurs. (2) when the overflow occurs, the active level specified in step (1) in the setting method is output. the active level is output until cr5n and the count of the 8-bit counter n (tm5n) match. (3) the pwm output after cr5n and the count match is the inactive level until an overflow occurs again. (4) steps (2) and (3) repeat until counting stops. (5) if counting is stopped by tce5n = 0, the pwm output goes to the inactive level. remarks: 1. n = 50, 51 2. tmc5n4 is only available at tm51. 1 tcen 1 tmcn6 00x lvsn lvrn tmcn1 toen tmcn x 0/1 1 ton output enable sets active level pwm mode tmn operation enable 8-bit timer/event counter mode tmcn4 147 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 figure 7-17: pwm output operation timing (active high setting) remark: n = 50, 51 figure 7-18: pwm output operation timings (crn0 = 00h, active high setting) remark: n = 50, 51 count clock tmn count value crn tcen inttmn ton 01 02 ff 00 01 02 n n+1 n+2 n+3 00 ovfn mn n 00 inactive level crn changing active level inactive level inactive level (m n) count clock tmn count value crn tcen inttmn ton 01 02 ff 00 01 02 ff 00 01 02 00 ovfn m00 00 00 inactive level crn changing (m 00) inactive level 148 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 figure 7-19: pwm output operation timings (crn = ffh, active high setting) remark: n = 50, 51 figure 7-20: pwm output operation timings (crn changing, active high setting) remark: n = 50, 51 caution: if crn is changed during tmn operation, the value changed is not reflected until tmn overflows. count clock tmn count value crn tcen inttmn ton 01 02 ff 00 01 02 ff 00 01 02 00 ovfn ff ff ff 00 inactive level inactive level active level inactive level active level count clock tmn count value crn0 tcen inttmn ton ovfn active level inactive level 00 ff n+2 n+1 n 02 01 00 ff 01 02 m+2 m+1 m m+3 00 active level inactive level crn changing n n mm (n m) 149 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 7.5 operation as interval timer (16-bit operation) (1) cascade (16-bit timer) mode (tm50 and tm51) the 16-bit resolution timer/counter mode is set by setting bit 4 (tmc514) of the 8-bit timer mode control register 51 (tmc51) to ? 1 ? . in this mode, tm50 and tm51 operate as a 16-bit interval timer that repeatedly generates an inter- rupt request at intervals specified by the count value set in advance to 8-bit compare registers 50 and 51 (cr50 and cr51). figure 7-21: 8-bit timer mode control register settings for 16-bit interval timer operation remark: 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. 1 tce51 0 tmc516 0 1 0/1 lvs51 lvr51 tmc511 toe51 tmc51 0/1 0/1 0 clear and start on match of tm50/tm51 and cr50/cr51 tm51 operation enable tmc514 16-bit timer/counter mode 1 tce50 0 tmc506 0 0 0/1 lvs50 lvr50 tmc501 toe50 tmc50 0/1 0/1 0/1 clear and start on match of tm50/tm51 and cr50/cr51 tm50 operation enable 150 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 151 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 figure 7-22 shows an example of timing in the 16-bit resolution cascade mode. figure 7-22: 16-bit resolution cascade mode (with tm50 and tm51) enables operation counting starts count clock tm50 tm51 tce51 to50 01h n n+1 00h 00h tce50 ffh 01h ffh 00h 00h n 00h 01h ffh cr50 cr51 m n inttm50 01h 02h m-1 m 00h a 00h b 00h interrupt request generated level inverted counter cleared operation stops interval time 00h 152 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 caution: the clock selection in the cascade mode (16-bit timer/event counter mode) is done by the register tcl50. remarks: 1. f x : main system clock oscillation frequency. 2. values in parentheses when operated at f x = 8.0 mhz. table 7-12: 8-bit timer/event counters interval times (16-bit timer/event counter mode) tcl502 tcl501 tcl500 minimum interval time maximum interval time resolution 0 0 0 ti50 input cycle 2 16 table 7-13: 8-bit timer/event counter square-wave output ranges (16-bit timer/event counter mode) tcl502 tcl501 tcl500 minimum pulse width maximum pulse width resolution 010 2 3 153 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 7.6 cautions on 8-bit timer/event counters 50 and 51 (1) timer start errors an error with a maximum of one clock might occur concerning the time required for a match signal to be generated after the timer starts. this is because 8-bit timer registers 50 and 51 are started asynchronously with the count pulse. figure 7-23: 8-bit timer registers 50 and 51 start timings remark: n = 50, 51 (2) compare registers 50 and 51 sets the 8-bit compare registers (cr50 and cr51) can be set to 00h. thus, when an 8-bit compare register is used as an event counter, one-pulse count operation can be carried out. figure 7-24: external event counter operation timings remark: n = 50, 51 count pulse tmn count value 00h timer start 01h 02h 03h 04h tin input crn 00h tmn count value 00h 00h 00h 00h ton interrupt request flag 154 chapter 7 8-bit timer/event counters 50 and 51 user ? s manual u16504ee1v1ud00 (3) operation after compare register change during timer count operation if the values after the 8-bit compare registers (cr50 and cr51) are changed are smaller than those of 8-bit timer registers (tm50 and tm51), tm50 and tm51 continue counting, overflow and then restarts counting from 0. thus, if the value (m) after cr50 and cr51 change is smaller than that (n) before change it is necessary to restart the timer after changing cr50 and cr51. figure 7-25: timings after compare register change during timer count operation remark: n = 50, 51 count pulse crn n x x-1 ffffh 0000h 0001h m 0002h tmn count value 155 user ? s manual u16504ee1v1ud00 chapter 8 8-bit timer 52 8.1 8-bit timer 52 functions the 8-bit timer 52 (tm52) has the following function: interval timer (1) 8-bit interval timer interrupts are generated at the preset time intervals. remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. 8.2 8-bit timer 52 configurations the 8-bit timer 52 consists of the following hardware. remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. table 8-1: 8-bit timer 52 interval times minimum interval width maximum interval width resolution 2 3 table 8-2: 8-bit timer 52 configurations item configuration timer register 8 bit (tm52) compare register 8 bit (cr52) timer output none control register timer clock select register 52 (tcl52) 8-bit timer mode control register 52 (tmc52) 156 chapter 8 8-bit timer 52 user ? s manual u16504ee1v1ud00 figure 8-1: 8-bit timer/event counter 52 block diagram note: the output signal of the timer tm52 can be used as clock input of the meter controller/driver. (1) compare register 52 (cr52) this 8-bit register compares the value with the count value of the 8-bit timer register 52 (tm52). if they match, an interrupt request (inttm52) is generated. cr52 is set with an 8-bit memory manipulation instruction. reset input sets cr52 value to 00h. (2) 8-bit timer register 52 (tm52) this 8-bit register counts pulses. tm52 is read with an 8-bit memory manipulation instruction. reset input sets tm52 to 00h. internal bus 8-bit compare register (cr50) match 8-bit timer register n (tm52) 4 clear internal bus tcl 522 tcl 521 tcl 520 timer clock select register 52 8-bit timer mode control register 52 inttm52 tce 52 selector fx/2 3 fx/2 4 fx/2 5 fx/2 7 fx/2 9 fx/2 11 output control circuit meter c/d note 157 chapter 8 8-bit timer 52 user ? s manual u16504ee1v1ud00 8.3 8-bit timer 52 control registers the following two types of registers are used to control the 8-bit timer 52. timer clock select register 52 (tcl52) 8-bit timer mode control register 52 (tmc52) (1) timer clock select register 52 (tcl52) this register sets the count clock of the 8-bit timer register 52. tcl52 is set with an 8-bit memory manipulation instruction. reset input sets tcl52 to 00h. figure 8-2: timer clock select register 52 format caution: when rewriting tcl52 to other data, stop the timer operation beforehand. remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. 76543210r/waddress after reset tcl5200000tcl522tcl521tcl520r/wff79h00h tcl522 tcl521 tcl520 8-bit timer register 52 count clock selection 010 f x /2 3 (1.0 mhz) 011 f x /2 4 (500 khz) 100 f x /2 5 (250 khz) 101 f x /2 7 (62.5 khz) 110 f x /2 9 (15.6 khz) 111 f x /2 11 (3.9 khz) other than above setting prohibited 158 chapter 8 8-bit timer 52 user ? s manual u16504ee1v1ud00 (2) 8-bit timer mode control register 52 (tmc52) this register enables/stops the operation of the 8-bit timer register 52. tmc52 is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets tmc52 to 04h. figure 8-3: 8-bit timer output control register format cautions: 1. timer operation must be stopped before setting tmc52. 2. be sure to set bit 0 to 0 and bit 2 to bit 6 to 0. remark: in case the timer tm52 is used as clock input of the meter c/d. the bit tmc521 has to be set to 1. <7>6543210r/waddress after reset tmc52 tce52 0 0 0 0 0 tmc521 0 r/w ff78h 00h tmc521 timer output f/f1 control 0 inversion operation disabled 1 inversion operation enabled tce52 8-bit timer register 50 operation control 0 operation stop (tm50 clear to 0) 1 operation enable 159 chapter 8 8-bit timer 52 user ? s manual u16504ee1v1ud00 8.4 8-bit timer 52 operations 8.4.1 interval timer operations setting the 8-bit timer mode control register (tmc52) as shown in figure 8-4 allows operation as an interval timer. an interrupt is generated repeatedly using the count value preset in the 8-bit compare register (cr52) as the interval. when the count value of the 8-bit timer register 52 (tm52) matches the value set to cr52, counting continues with the tm52 value cleared to 0 and the interrupt request signal inttm52 is generated. count clock of the 8-bit timer register 52 (tm52) can be selected with the timer clock select register 52 (tcl52). figure 8-4: 8-bit timer mode control register settings for interval timer operation figure 8-5: interval timer operation timings (1/3) (a) when n = 00h to ffh remark: interval time = (n + 1) x t: n = 00h to ffh 1 tce52 0000 tmc52 00 0 tm52 operation enable t 00 01 n 00 01 n 00 01 n n n n n clear clear count start interrupt acknowledge interrupt acknowledge interval time interval time interval time count clock tm52 count value cr52 tce52 inttm52 160 chapter 8 8-bit timer 52 user ? s manual u16504ee1v1ud00 figure 8-5: interval timer operation timings (2/3) (b) when cr52 = 00h (c) when cr52 = ffh t count clock tm52 cr52 tce52 inttm52 interval time 00h 00h 00h 00h 00h t count clock tm52 cr52 tce52 inttm52 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt received interrupt received 161 chapter 8 8-bit timer 52 user ? s manual u16504ee1v1ud00 figure 8-5: interval timer operation timings (3/3) (d) operated by cr52 transition (m < n) (e) operated by cr52 transition (m > n) count clock tm52 cr52 tce52 inttm52 00h n n m n ffh 00h m 00h m cr52 transition tm52 overflows since m < n count clock tm52 cr52 tce52 inttm52 n n 00h 01h n 1 m 00h 01h m cr52 transition 162 user ? s manual u16504ee1v1ud00 [memo] 163 user ? s manual u16504ee1v1ud00 chapter 9 watch timer 9.1 watch timer functions the watch timer has the following functions: watch timer interval timer the watch timer and the interval timer can be used simultaneously. the figure 9-1 shows watch timer block diagram. figure 9-1: block diagram of watch timer f x /2 7 f f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 0 wtm1 wtm0 watch timer mode control register (wtm) internal bus selector selector selector wtm3 /2 x 11 164 chapter 9 watch timer user ? s manual u16504ee1v1ud00 (1) watch timer when the main system clock or subsystem clock is used, interrupt requests (intwt) are generated at 0.25 second intervals. (2) interval timer interrupt requests (intwti) are generated at the preset time interval. remarks: 1. f x : main system clock oscillation frequency 2. f w : watch timer clock frequency 9.2 watch timer configuration the watch timer consists of the following hardware. table 9-1: interval timer interval time interval time when operated at f x = 8.00 mhz when operated at f x = 4.00 mhz 2 4 /f w 256 s 512 s 2 5 /f w 512 s 1 ms 2 6 /f w 1 ms 2 ms 2 7 /f w 2 ms 4 ms 2 8 /f w 4 ms 8.19 ms 2 9 /f w 8.19 ms 16.3 ms table 9-2: watch timer configuration item configuration counter 5 bits 165 chapter 9 watch timer user ? s manual u16504ee1v1ud00 9.3 watch timer mode register (wtm) this register sets the watch timer count clock, the watch timer operating mode, and prescaler interval time and enables/disables prescaler and 5-bit counter operations. wtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets wtm to 00h. figure 9-2: watch timer mode control register (wtm) format (1/2) 76543210r/waddress after reset wtm wtm7 wtm6 wtm5 wtm4 wtm3 0 wtm1 wtm0 r/w ff41h 00h wtm7 watch timer count clock selection 0 input clock set to f x / 2 7 1 input clock set to f x / 2 11 wtm6 wtm5 wtm4 prescaler interval time selection f x = 8.00 mhz operation f w =f x /2 7 f x = 4.00 mhz operation f w =f x /2 7 000 2 4 /f w (256 s) 2 4 /f w (512 s) 001 2 5 /f w (512 s) 2 5 /f w w (1 ms) 010 2 6 /f w (1 ms) 2 6 /f w (2 ms) 011 2 7 /f w (2 ms) 2 7 /f w (4 ms) 100 2 8 /f w (4 ms) 2 8 /f w (8.19 ms) 101 2 9 /f w (8.19 ms) 2 9 /f w (16.38 ms) other than above setting prohibited wtm3 watch operating mode selections 0 normal operating mode (interrupt generation at 2 14 /f w ) 1 fast feed operating mode (interrupt generation at 2 5 /f w ) ? 166 chapter 9 watch timer user ? s manual u16504ee1v1ud00 figure 9-2: watch timer mode control register (wtm) format (2/2) caution: when the watch timer is used, the prescaler should not be cleared frequently. when rewriting wtm4 to wtm6 to other data, stop the timer operation beforehand. remarks: 1. f w : watch timer clock frequency (f x /2 7 or f x /2 11 ) 2. f x : main system clock oscillation frequency wtm1 5-bit counter operation control 0 clear after operation stop 1 operation enable wtm0 prescaler operation control 0 clear after operation stop 1 operation enable 167 chapter 9 watch timer user ? s manual u16504ee1v1ud00 9.4 watch timer operations 9.4.1 watch timer operation when the 8.00-mhz main system clock is used, the timer operates as a watch timer and generates interrupt requests at a constant time interval. when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer mode control register (wtm) are set to 1, the count operation starts. when set to 0, the 5-bit counter is cleared and the count operation stops. for simultaneous operation of the interval timer, zero-second start can be only the watch timer by setting wtm1 to 0. however, since the 9-bit prescaler is not cleared the first overflow of the watch timer (intwt) after zero-second start may include an error of up to 2 9 table 9-3: interval timer operation wtm6 wtm5 wtm4 interval time f x = 8.00 mhz operation f x = 4.00 mhz operation 000 2 4 168 chapter 9 watch timer user ? s manual u16504ee1v1ud00 figure 9-3: operation timing of watch timer/interval timer remark: f w : watch timer clock frequency 0h start overflow overflow 5-bit counter count clock f w watch timer interrupt intwt interval timer interrupt time of watch timer interval timer (t) t interrupt time of watch timer interrupt intwti 169 user ? s manual u16504ee1v1ud00 chapter 10 watchdog timer 10.1 watchdog timer functions the watchdog timer has the following functions: watchdog timer interval timer caution: select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (wdtm). (1) watchdog timer mode upon detection of an inadvertent program loop, a non-maskable interrupt request or reset can be generated. remark: figures in parentheses apply to operation with f x = 8.0 mhz. table 10-1: watchdog timer inadvertent program overrun detection times runaway detection time 2 12 170 chapter 10 watchdog timer user ? s manual u16504ee1v1ud00 (2) interval timer mode interrupts are generated at the preset time intervals. remark: figures in parentheses apply to operation with f x = 8.0 mhz. table 10-2: interval times interval time 2 12 171 chapter 10 watchdog timer user ? s manual u16504ee1v1ud00 10.2 watchdog timer configuration the watchdog timer consists of the following hardware. figure 10-1: watchdog timer block diagram table 10-3: watchdog timer configuration item configuration control register timer clock select register (wdcs) watchdog timer mode register (wdtm) prescaler f x 2 4 f x 2 5 f x 2 6 f x 2 7 f x 2 8 f x 2 9 selector watchdog timer mode register internal bus internal bus wdcs2 wdcs1 wdcs0 f x /2 12 f x 2 11 watchdog timer clock selection register 3 wdtm4 wdtm3 8-bit counter wdtmk run wdtif intwdt maskable interrupt request reset intwdt non-maskable interrupt request control circuit 172 chapter 10 watchdog timer user ? s manual u16504ee1v1ud00 10.3 watchdog timer control registers the following two types of registers are used to control the watchdog timer. watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) (1) watchdog timer clock select register (wdcs) this register sets the watchdog timer count clock. wdcs is set with 8-bit memory manipulation instruction. reset input sets wdcs to 00h. figure 10-2: timer clock select register 2 format caution: when rewriting wdcs to other data, stop the timer operation beforehand. remarks: 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.0 mhz. 76543210r/waddress after reset wdcs 0 0 0 0 0 wdcs2 wdcs1 wdcs0 r/w ff42h 00h wdcs2 wdcs1 wdcs0 overflow time of watchdog timer 000 f x /2 12 (512 s) 001 f x /2 13 (1 ms) 010 f x /2 14 (2 ms) 011 f x /2 15 (4 ms) 100 f x /2 16 (8.19 ms) 101 f x /2 17 (16.38 ms) 110 f x /2 18 (32.76 ms) 111 f x /2 20 (131 ms) 173 chapter 10 watchdog timer user ? s manual u16504ee1v1ud00 (2) watchdog timer mode register (wdtm) this register sets the watchdog timer operating mode and enables/disables counting. wdtm is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets wdtm to 00h. figure 10-3: watchdog timer mode register format notes: 1. once set to 1, wdtm3 and wdtm4 cannot be cleared to 0 by software. 2. once set to 1, run cannot be cleared to 0 by software. thus, once counting starts, it can only be stopped by reset input. caution: when 1 is set in run so that the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by watchdog timer clock select register. remark: x = don't care. <7>6543210r/waddress after reset wdtm run 0 0 wdtm4 wdtm3 0 0 0 r/w fff9h 00h wdtm4 wdtm3 watchdog timer operation mode selection note 1 0x interval timer mode (maskable interrupt occurs upon generation of an overflow) 10 watchdog timer mode 1 (non-maskable interrupt occurs upon generation of an overflow) 11 watchdog timer mode 2 (reset operation is activated upon generation of an overflow) run watchdog timer operation mode selection note 2 0 count stop 1 counter is cleared and counting starts 174 chapter 10 watchdog timer user ? s manual u16504ee1v1ud00 10.4 watchdog timer operations 10.4.1 watchdog timer operation when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. the watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (wdcs0 to wdcs2) of the timer clock select register (wdcs). watchdog timer starts by setting bit 7 (run) of wdtm to 1. after the watchdog timer is started, set run to 1 within the set overrun detection time interval. the watchdog timer can be cleared and count- ing is started by setting run to 1. if run is not set to 1 and the inadvertent program loop detection time is past, system reset or a non-maskable interrupt request is generated according to the wdtm bit 3 (wdtm3) value. the watchdog timer can be cleared when run is set to 1. the watchdog timer continues operating in the halt mode but it stops in the stop mode. thus, set run to 1 before the stop mode is set, clear the watchdog timer and then execute the stop instruc- tion. cautions: 1. the actual overrun detection time may be shorter than the set time by a maximum of 0.5%. 2. when the subsystem clock is selected for cpu clock, watchdog timer count oper- ation is stopped. remarks: 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.0 mhz. table 10-4: watchdog timer overrun detection time wdcs2 wdcs1 wdcs0 runaway detection time 000 f x /2 12 (512 s) 001 f x /2 13 (1 ms) 010 f x /2 14 (2 ms) 011 f x /2 15 (4 ms) 100 f x /2 16 (8.19 ms) 101 f x /2 17 (16.38 ms) 110 f x /2 18 (32.76 ms) 111 f x /2 20 (131 ms) 175 chapter 10 watchdog timer user ? s manual u16504ee1v1ud00 10.4.2 interval timer operation the watchdog timer operates as an interval timer which generates interrupts repeatedly at an interval of the preset count value when bit 3 (wdtm3) of the watchdog timer mode register (wdtm) is set to 0, respectively. when the watchdog timer operates as interval timer, the interrupt mask flag (tmmk4) and priority specify flag (tmpr4) are validated and the maskable interrupt request (intwdt) can be generated. among maskable interrupts, the intwdt default has the highest priority. the interval timer continues operating in the halt mode but it stops in stop mode. thus, set bit 7 (run) of wdtm to 1 before the stop mode is set, clear the interval timer and then execute the stop instruction. cautions: 1. once bit 4 (wdtm4) of wdtm is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless reset input is applied. 2. the interval time just after setting with wdtm may be shorter than the set time by a maximum of 0.5%. 3. when the subsystem clock is selected for cpu clock, watchdog timer count operation is stopped. remarks: 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.0 mhz. table 10-5: interval timer interval time wdcs2 wdcs1 wdcs0 interval time 000 f x /2 12 (512 s) 001 f x /2 13 (1 ms) 010 f x /2 14 (2 ms) 011 f x /2 15 (4 ms) 100 f x /2 16 (8.19 ms) 101 f x /2 17 (16.38 ms) 110 f x /2 18 (32.76 ms) 111 f x /2 20 (131 ms) 176 user ? s manual u16504ee1v1ud00 [memo] 177 user ? s manual u16504ee1v1ud00 chapter 11 clock output control circuit 11.1 clock output control circuit functions the clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral lsi. clocks selected with the clock output selection register (cks) are output from the pcl/p61/sgoa pin. follow the procedure below to route clock pulses to the sgoa pin: (1) select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (ccs0 to ccs2) of cks. (2) set the p61 output latch to 0. (3) set bit 1 (pm61) of port mode register 6 to 0 (set to output mode). (4) set bit 4 (cloe) of clock output selection register to 1. caution: clock output cannot be used when setting p61 output latch to 1. remark: when clock output enable/disable is switched, the clock output control circuit does not generate pulses with smaller widths than the original signal carries. (see the portions marked with * in figure 10-1). figure 11-1: remote controlled output application example cloe pcl/p61/sgoa * * pin output 178 chapter 11 clock output control circuit user ? s manual u16504ee1v1ud00 11.2 clock output control circuit configuration the clock output control circuit consists of the following hardware. figure 11-2: clock output control circuit block diagram table 11-1: clock output control circuit configuration item configuration control register clock output selection register (cks) port mode register 6 (pm6) internal bus f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 cloe ccs2 ccs1 ccs0 p61 output latch synchronizing circuit 4 pm61 selector clock output selection register port mode register 6 pcl /p61/sgoa 179 chapter 11 clock output control circuit user ? s manual u16504ee1v1ud00 11.3 clock output function control registers the following two types of registers are used to control the clock output function. clock output selection register (cks) port mode register 6 (pm6) (1) clock output selection register (cks) this register sets pcl output clock. cks is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets cks to 00h. caution: when enabling pcl output, set ccs0 to ccs2, then set 1 in cloe with an 1-bit memory manipulation instruction. figure 11-3: timer clock select register 0 format remarks: 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.0 mhz. 765<4>3210r/waddress after reset cks 0 0 0 cloe 0 ccs2 ccs1 ccs0 r/w ff40h 00h ccs2 ccs1 ccs0 pcl output clock selection 000 f x (8 mhz) 001 f x /2 1 (4 mhz) 010 f x /2 2 (2 mhz) 011 f x /2 3 (1 mhz) 100 f x /2 4 (500 khz) 101 f x /2 5 (250 khz) 110 f x /2 6 (125 khz) 111 f x /2 7 (62.5 khz) other than above setting prohibited cloe pcl output control 0 output disable 1 output enable 180 chapter 11 clock output control circuit user ? s manual u16504ee1v1ud00 (2) port mode register 6 (pm6) with this register the port mode pm3 can be set bit-wise. when using the p61/pcl/sgoa pin for clock output function, set pm61 and output latch of p61 to 0. pm6 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm6 to ffh. figure 11-4: port mode register 6 format 76543210r/waddress after reset pm6 0 0 pm65 pm64 pm63 pm62 pm61 pm60 r/w ff26h ffh pm6n pm6n pin input/output mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) 181 user ? s manual u16504ee1v1ud00 chapter 12 a/d converter 12.1 a/d converter functions the a/d converter is an 8-bit resolution converter that converts analog input voltages into digital values. it can control up to 5 analog input channels (ani0 to ani4). this a/d converter has the following functions: (1) a/d conversion with 8-bit resolution with the analog input channel specification register (ads1) one out of 5 analog input channels is selected. conversion time and start of sampling is controlled by the a/d converter mode register (adm). each time the conversion has been completed, an interrupt request (intad) is generated. (2) power-fail detection function the result of an a/d conversion (value of the adcr1 register) and the value of pft register (pft: power-fail compare threshold value register) are compared. if the condition for comparison is satisfied, the intad is generated. figure 12-1: a/d converter block diagram ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 selector sample & hold circuit voltage comparator successive approximation register (sar) control circuit 3 a/d conversion result register (adcr1) tap selector av dd /av ref avss intad a/d converter mode register analog input channel specification register internal bus ads12 ads11 ads10 adcs1 fr12 fr11 fr10 182 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 figure 12-2: power-fail detection function block diagram 12.2 a/d converter configuration a/d converter consists of the following hardware. (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string, and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is set (end of a/d conversion), the sar contents are transferred to the a/d conversion result register. table 12-1: a/d converter configuration item configuration analog input 5 channels (ani0 to ani4) registers successive approximation register (sar) a/d conversion result register (adcr1) control registers a/d converter mode register (adm1) analog input channel specification register (ads1) power-fail compare mode register (pfm) power-fail compare threshold value register (pft) ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 multiplex er selector a/d converter internal bus power-fail compare mode register (pfm) comparator pfen pfcm power-fail compare threshold value register (pft) intad pfen pfcm 183 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 (2) a/d conversion result register (adcr1) this register holds the a/d conversion result. each time when the a/d conversion ends, the con- version result is loaded from the successive approximation register. adcr1 is read with an 8-bit memory manipulation instruction. reset input clears adcr1 to 00h. caution: if a write operation is executed to the a/d converter mode register (adm1) and the analog input channel specification register (ads1), the contents of adcr1 are unde- fined. read the conversion result before a write operation is executed to adm1 and ads1. if a timing other than the above is used, the correct conversion result may not be read. (3) sample & hold circuit the sample & hold circuit samples each analog input sequential applied from the input circuit, and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value dur- ing a/d conversion. (4) voltage comparator the voltage comparator compares the analog input to the series resistor string output voltage. (5) series resistor string the series resistor string is in av dd to av ss , and generates a voltage to be compared to the ana- log input. (6) ani0 to ani4 pins these are five analog input pins to feed analog signals to the a/d converter. ani0 to ani4 are alternate-function pins that can also be used for digital input. caution: use ani0 to ani4 input voltages within the specified range. if a voltage higher than av dd or lower than av ss is applied (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (7) av dd pin (shared with av ref pin) this pin supplies the a/d converter reference voltage and is used as the power supply pin of the a/ d-converter. it converts signals from ani0 to ani4 into digital signals according to the voltage applied between av dd and av ss . keep the av dd /av ref pin always at the same potential as the v dd pin, even when the a/d-con- verter is not used. (8) av ss pin this is the gnd potential pin of the a/d converter. always keep it at the same potential as the v ss pin even when not using the a/d converter. 184 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 12.3 a/d converter control registers the following 4 types of registers are used to control a/d converter. a/d converter mode register (adm1) analog input channel specification register (ads1) power-fail compare mode register (pfm) power-fail compare threshold value register (pft) (1) a/d converter mode register (adm1) this register sets the conversion time for analog input to be a/d converted, conversion start/stop, and external trigger. adm1 is set with an 1-bit or an 8-bit memory manipulation instruction. reset input clears adm1 to 00h. figure 12-3: a/d converter mode register (adm1) format note: set so that the a/d conversion time is 14 s or more. caution: bits 0 to 2 and bit 6 must be set to 0. remark: f x : main system clock oscillation frequency. <7>6543210r/waddress after reset adm1 adcs1 0 fr12 fr11 fr10 0 0 0 r/w ff98h 00h adcs1 a/d conversion operation control 0 stop conversion operation 1 enable conversion operation fr12 fr11 fr10 conversion time selection note 000 144/f x 001 120/f x 010 96/f x 100 288/f x 101 240/f x 110 192/f x other than above setting prohibited 185 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 (2) analog input channel specification register (ads1) this register specifies the analog voltage input port for a/d conversion. ads1 is set with an 8-bit memory manipulation instruction. reset input clears ads1 to 00h. figure 12-4: analog input channel specification register (ads1) format caution: bits 3 to 7 must be set to 0. 76543210r/waddress after reset ads1 0 0 0 0 0 ads12 ads11 ads10 r/w ff99h 00h ads12 ads11 ads10 analog input channel specification 000 ani0 001 ani1 010 ani2 011 ani3 100 ani4 other than above setting prohibited 186 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 (3) power-fail compare mode register (pfm) the power-fail compare mode register (pfm) controls a comparison operation. pfm is set with an 1-bit or an 8-bit memory manipulation instruction. reset input clears pfm to 00h. figure 12-5: power-fail compare mode register (pfm) format caution: bits 0 to 5 must be set to 0. (4) power-fail compare threshold value register (pft) the power-fail compare threshold value register (pft) sets a threshold value against which the result of a/d conversion is to be compared. pft is set with an 8-bit memory manipulation instruction. reset input clears pft to 00h. figure 12-6: power-fail compare threshold value register (pft) 76543210r/waddress after reset pfmpfenpfcm000000r/wff9ah00h pfen enables power-fail comparison 0 disables power-fail comparison (used as normal a/d converter) 1 enables power-fail comparison (used to detect power failure) pfcm power-fail compare mode selection 0 adcr1 187 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 12.4 a/d converter operations 12.4.1 basic operations of a/d converter <1> select one channel for the a/d conversion with the analog input channel specification register (ads1). <2> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the analog input voltage is held until the a/d conversion operation is complete. <4> upon completion of the comparison of 8-bits, the digital result of the a/d conversion resides in sar. the result is latched in the a/d conversion result register (adcr1). at the same time, the a/d conversion end interrupt request (intad) can also be generated. caution: the first a/d conversion value just after starting the a/d conversion (adcs1=1) is undefined. figure 12-7: basic operation of 8-bit a/d converter a/d conversion operations are performed continuously until bit 7 (adcs1) of the a/d converter mode register (adm1) is reset (to 0) by software. if a write operation to the adm1 and analog input channel specification register (ads1) is performed during an a/d conversion operation, the conversion operation is initialized, and if the adcs1 bit is set (to 1), conversion starts again from the beginning. reset input sets the a/d conversion result register (adcr1) to 00h. conv ersion time sampling time sampling a/d conv ersion undefined 80h c0h or 40h conversion result a/d converter operation sar adcr1 intad conversion result ? 188 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 12.4.2 input voltage and conversion results the relation between the analog input voltage input to the analog input pins (ani0 to ani4) and the a/d conversion result (stored in the a/d conversion result register (adcr1)) is given by the following expression. or where, int( ) : function which returns integer part of value in parentheses v in : analog input voltage av dd :av dd pin voltage adcr1 : a/d conversion result register (adcr1) value figure 12-8, ? relation between analog input voltage and a/d conversion result, ? on page 189 shows the relation between the analog input voltage and the a/d conversion result. v in av dd ? 0.5) 189 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 figure 12-8: relation between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcr1) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av dd 190 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 12.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one analog input channel is selected from among ani0 to ani4 with the analog input channel specification register (ads1) and a/d conversion is performed when bit adcs1 in adm1 is set to 1. the following two types of functions can be selected by setting the pfen flag of the pfm register. normal 8-bit a/d converter (pfen = 0) power-fail detection function (pfen = 1) (1) a/d conversion (when pfen = 0) when bit 7 (adcs1) of the a/d converter mode register (adm1) is set to 1 and bit 7 of the power- fail compare mode register (pfm) is set to 0, a/d conversion of the voltage applied to the analog input pin specified with the analog input channel specification register (ads1) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr1), and the interrupt request signal (intad) is generated. after one a/d conversion operation has ended, the next conversion operation is immediately started. a/d conversion opera- tions are repeated until new data is written to ads1. if ads1 is rewritten during a/d conversion operation, the a/d conversion operation under execu- tion is stopped, and a/d conversion of a newly selected analog input channel is started. if data with adcs1 set to 0 is written to adm1 during a/d conversion operation, the a/d conver- sion operation stops immediately. (2) power-fail detection function (when pfen = 1) when bit 7 (adcs1) of the a/d converter mode register (adm1) and bit 7 (pfen) of the power-fail compare mode register (pfm) are set to 1, a/d conversion of the voltage applied to the analog input pin specified with the analog input channel specification register (ads1) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr1), compared with the value of the power-fail compare threshold value register (pft), and intad is generated under the condition specified by the pfcm flag of the pfm regis- ter. caution: when executing power-fail comparison, the interrupt request signal (intad) is not generated on completion of the first conversion after adcs1 has been set to 1. intad is valid from completion of the second conversion. 191 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 figure 12-9: a/d conversion remarks: 1. n = 0, 1, ..., 4 2. m = 0, 1, ..., 4 adm1 rewrite adcs1 = 1 ads1 rewrite adcs1 = 0 a/d conversion adcr1 intad (pfen = 0) intad (pfen = 1) anin anin anin anim anim stop anin anin anim conversion suspended; conversion results are not stored first conversion condition satisfied 192 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 12.5 a/d converter precautions (1) current consumption in standby mode a/d converter stops operating in the standby mode. at this time, current consumption can be reduced ( figure 12-10: example method of reducing current consumption in standby mode (2) input range of ani0 to ani4 the input voltages of ani0 to ani4 should be within the specification range. in particular, if a voltage higher than av dd or lower than av ss is input (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) contending operations (a) contention between a/d conversion result register (adcr1) write and adcr1 read by instruction upon the end of conversion adcr1 read is given priority. after the read operation, the new conversion result is written to adcr1. (b) contention between adcr1 write and a/d converter mode register (adm1) write or analog input channel specification register (ads1) write upon the end of conversion adm1 or ads1 write is given priority. adcr1 write is not performed, nor is the conversion end interrupt request signal (intad) generated. av dd av ss p-ch series resistor string ( ~ 21 k w ) adcs1 av dd av ref ad-converter power supply 193 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 (4) noise counter measures to maintain 8-bit resolution, attention must be paid to noise input to pin av dd and pins ani0 to ani4. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 11-11 to reduce noise. figure 12-11: analog input pin handling (5) ani0 to ani4 the analog input pins (ani0 to ani4) also function as input port pins (p10 to p14). when a/d conversion is performed with any of pins ani0 to ani4 selected, do not execute a port input instruction while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (6) av dd /av ref pin input impedance a series resistor string of approximately 21 k ? 194 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 (7) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the analog input channel specification reg- ister (ads1) is changed. caution is therefore required if a change of analog input pin is performed during a/d conversion. the a/d conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ads1 rewrite. if the adif is read immediately after the ads1 rewrite, the adif may be set despite the fact that the a/d conversion for the post-change analog input has not ended. when the a/d conversion is stopped and then resumed, clear adif before the a/d conversion operation is resumed. figure 12-12: a/d conversion end interrupt request generation timing remarks: 1. n = 0, 1, ..., 4 2. m = 0, 1, ..., 4 (8) read of a/d conversion result register (adcr1) when a write operation is executed to a/d converter mode register (adm1) and analog input channel specification register (ads1), the contents of adcr1 are undefined. read the conversion result before write operation is executed to adm1, ads1. if a timing other than the above is used, the correct conversion result may not be read. ads1 rewrite (start of anin conversion) a/d conversion adcr1 intad anin anin anim anim anin anin anim anim ads1 rewrite (start of anim conversion) adif is set but anim conversion has not ended. 195 chapter 12 a/d converter user ? s manual u16504ee1v1ud00 12.6 cautions on emulation to perform debugging with an in-circuit emulator, the d/a converter mode register (dam0) must be set. dam0 is a register used to set the i/o board (ie-78k0-ns-p04). 12.6.1 d/a converter mode register (dam0) dam0 is necessary if the power-fail detection function is used. unless dam0 is set, the power-fail detection function cannot be used. dam0 is a write-only register. because the ie-78k0-ns-p04 uses an external analog comparator and a d/a converter to implement part of the power-fail detection function, the reference voltage must be controlled. therefore, set bit 0 (dace) of dam0 to 1 when using the power-fail detection function. figure 12-13: d/a converter mode register (dam0) format cautions: 1. dam0 is a special register that must be set when debugging is performed with an in-circuit emulator. even if this register is used, the operation of the pd780828a subseries is not affected. however, delete the instruction that manipulates this register from the program at the final stage of debugging. 2. bits 7 to 1 must be set to 0. 76543210r/waddress after reset dam00000000dacer/wff9ch00h dace reference voltage control 0 disabled 1 enabled (when power-fail detection function is used) 196 user ? s manual u16504ee1v1ud00 [memo] 197 user ? s manual u16504ee1v1ud00 chapter 13 serial interface sio30 13.1 sio30 functions the sio30 has the following two modes. operation stop mode 3-wire serial i/o mode (1) operation stop mode this mode is used if serial transfer is not performed. for details, see 13.5.1 ? operation stop mode ? on page 200 . (2) 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck30), serial output line (so30), and serial input line (si30). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfers is reduced. the first bit in the 8-bit data in serial transfers is fixed as the msb. 3-wire serial i/o mode is useful for connection to a peripheral i/o device that includes a clock-syn- chronous serial interface, like a display controller, etc. for details see 13.5.2 ? three-wire serial i/o mode ? on page 201 . figure 13-1 shows a block diagram of the sio30. figure 13-1: block diagram of sio30 internal bus 8 8 direction control circuit serial clock control circuit serial clock counter interruption request signal generator selector serial i/o shift register 30 (sio30) si30/p37/s24 so30/p36/s25 sck30/p35/s26 intcsi30 f x /2 2 f x /2 3 f x /2 4 csie30 mode31 scl301 scl300 register csim30 198 chapter 13 serial interface sio30 user ? s manual u16504ee1v1ud00 13.2 sio30 configuration the sio30 includes the following hardware. (1) serial i/o shift register (sio30) this is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. sio30 is set by an 8-bit memory manipulation instruction. when ? 1 ? is set to bit 7 (csie30) of the serial operation mode register (csim30), a serial operation can be started by writing data to or reading data from sio30. when transmitting, data written to sio30 is output via the serial output (so30). when receiving, data is read from the serial input (si30) and written to sio30. the reset signal resets the register value to 00h. caution: do not access sio30 during a transmit operation unless the access is triggered by a transfer start. (read is disabled when mode30 = 0 and write is disabled when mode30 = 1.) 13.3 list of sfrs (special function registers) table 13-1: composition of sio30 item configuration registers serial i/o shift register (sio30) control registers serial operation mode register (csim30) table 13-2: list of sfrs (special function registers) sfr name symbol r/w units available for bit manipulation value after reset 1-bit 8-bit 16-bit serial operation mode register csim30 r/w 199 chapter 13 serial interface sio30 user ? s manual u16504ee1v1ud00 13.4 serial interface control register the sio30 uses the following type of register for control functions. serial operation mode register (csim30) serial operation mode register (csim30) this register is used to enable or disable the serial clock, selects operation modes, and defines specific operations. csim30 can be set via a 1-bit or 8-bit memory manipulation instruction. the reset input sets the value to 00h. figure 13-2: format of serial operation mode register (csim30) notes: 1. when csie30 = 0 (sio30 operation stop status), the pins connected to si30 and so30 can be used for port functions. 2. when mode30 = 1 (receive mode), pin p36 can be used for port function. <7>6543210r/waddress after reset csim30 csie30 0 0 0 0 mode30 scl301 scl300 r/w ffa8h 00h csie30 enable/disable specification for sio30 shift register operation serial counter port note 1 0 operation stop clear port function 1 operation enable count operation enable serial operation + port function mode30 transfer operation modes and flags operation mode transfer start trigger so30/p36 0 transmit/receive mode write to sio30 so30 output 1 receive-only mode note 2 read from sio30 port function scl301 scl300 clock selection (f x = 8.00 mhz) 0 0 external clock input 01 f x /2 2 10 f x /2 3 11 f x /2 4 200 chapter 13 serial interface sio30 user ? s manual u16504ee1v1ud00 13.5 serial interface operations this section explains two modes of sio30. 13.5.1 operation stop mode this mode is used if the serial transfers are not performed to reduce power consumption. during the operation stop mode, the pins can be used as normal i/o ports as well. register settings the operation stop mode can be set via the serial operation mode register (csim30). csim30 can be set via 1-bit or 8-bit memory manipulation instructions. the reset input sets the value to 00h. figure 13-3: format of serial operation mode register (csim30) note: when csie30 = 0 (sio30 operation stop status), the pins si30, so30 and sck30 can be used for port functions. <7>6543210r/waddress after reset csim30 csie30 0 0 0 0 mode30 scl301 scl300 r/w ffa8h 00h csie30 sio30 operation enable/disable specification shift register operation serial counter port 0 operation stop clear port function note 1 1 operation enable count operation enable serial operation + port function 201 chapter 13 serial interface sio30 user ? s manual u16504ee1v1ud00 13.5.2 three-wire serial i/o mode the three-wire serial i/o mode is useful when connecting a peripheral i/o device that includes a clock-synchronous serial interface, a display controller, etc. this mode executes the data transfer via three lines: a serial clock line (sck30 ), serial output line (so30), and serial input line (si30). (1) register settings the 3-wire serial i/o mode is set via serial operation mode register (csim30). csim30 can be set via 1-bit or 8-bit memory manipulation instructions. the reset input set the value to 00h. figure 13-4: format of serial operation mode register (csim30) notes: 1. when csie30 = 0 (sio30 operation stop status), the pins si30, so30 and sck30 can be used for port functions. 2. when csie30 = 1 (sio30 operation enabled status), the si30 pin can be used as a port pin if only the send function is used, and the so30 pin can be used as a port pin if only the receive-only mode is used. caution: in the 3-wire serial i/o mode, set the port mode register (pm3) as required. set the output latch of the port to 0. <7>6543210r/waddress after reset csim30 csie30 0 0 0 0 mode30 scl301 scl300 r/w ffa8h 00h csie30 enable/disable specification for sio30 shift register operation serial counter port 0 operation stop clear port function note 1 1 operation enable count operation enable serial operation + port function note 2 mode30 transfer operation modes and flags operation mode transfer start trigger so30/p36 0 transmit/receive mode write to sio30 so30 output 1 receive-only mode note 2 read from sio30 port function scl301 scl300 clock selection (f x = 8.00 mhz) 0 0 external clock input 01 f x /2 2 10 f x /2 3 11 f x /2 4 202 chapter 13 serial interface sio30 user ? s manual u16504ee1v1ud00 203 chapter 13 serial interface sio30 user ? s manual u16504ee1v1ud00 (3) transfer start a serial transfer starts when the following conditions have been satisfied and transfer data has been set to serial i/o shift register 30 (sio30). the sio30 operation control bit must be set (csie = 1) in transmit/receive mode when csie30 = 1 and mode30 = 0, transfer starts when writing to sio30. in receive-only mode when csie30 = 1 and mode30 = 1, transfer starts when reading from sio30. caution: after the data has been written to sio30, the transfer will not start even if the csie30 bit value is set to ? 1 ? . the completion of an 8-bit transfer automatically stops the serial transfer operation and sets a serial transfer completion flag. after an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. 204 user ? s manual u16504ee1v1ud00 [memo] 205 user ? s manual u16504ee1v1ud00 chapter 14 serial interface sio31 14.1 sio31 functions the sio31 has the following three modes. operation stop mode 3-wire serial i/o mode 2-wire serial i/o mode (1) operation stop mode this mode is used if serial transfer is not performed. for details, see 14.5.1 ? operation stop mode ? on page 210 . (2) 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck31), serial output line (so31), and serial input line (si31). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfers is reduced. the first bit in the 8-bit data in serial transfers is fixed as the msb. 3-wire serial i/o mode is useful for connection to a peripheral i/o device that includes a clock-syn- chronous serial interface, like a display controller, etc. for details see 14.5.2 ? three-wire serial i/o mode ? on page 211 . (3) 2-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using two lines: a serial clock line (sck31) and a serial data input/output line (sio31). the first bit in the 8-bit data in serial transfers is fixed as the msb. 206 chapter 14 serial interface sio31 user ? s manual u16504ee1v1ud00 figure 14-1 shows a block diagram of the sio31. figure 14-1: block diagram of sio31 internal bus 8 8 direction control circuit serial clock control circuit serial clock counter interruption request signal generator selector serial i/o shift register 31 (sio31) si31/p95/s18 so31/sio31/p94/s19 sck31/p93/s20 intcsi31 tm50 f x /2 3 f x /2 7 csie31 mode31 scl311 scl310 register csim31 selector 207 chapter 14 serial interface sio31 user ? s manual u16504ee1v1ud00 14.2 sio31 configuration the sio31 includes the following hardware. (1) serial i/o shift register (sio31) this is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. sio31 is set by an 8-bit memory manipulation instruction. when ? 1 ? is set to bit 7 (csie31) of the serial operation mode register (csim31), a serial operation can be started by writing data to or reading data from sio31. when transmitting, data written to sio31 is output via the serial output (so31). when receiving, data is read from the serial input (si31) and written to sio31. the reset signal resets the register value to 00h. caution: do not access sio31 during a transmit operation unless the access is triggered by a transfer start. (read is disabled when mode31 = 0 and write is disabled when mode31 = 1.) 14.3 list of sfrs (special function registers) table 14-1: composition of sio31 item configuration registers serial i/o shift register (sio31) control registers serial operation mode register (csim31) serial mode switch register (sioswi) table 14-2: list of sfrs (special function registers) sfr name symbol r/w units available for bit manipulation value after reset 1-bit 8-bit 16-bit serial operation mode register csim31 r/w 208 chapter 14 serial interface sio31 user ? s manual u16504ee1v1ud00 14.4 serial interface control register the sio31 uses the following type of register for control functions. serial operation mode register (csim31) serial mode switch register (sioswi) (1) serial operation mode register (csim31) this register is used to enable or disable the serial clock, selects operation modes, and defines specific operations. csim31 can be set via an 1-bit or an 8-bit memory manipulation instruction. the reset input sets the value to 00h. figure 14-2: format of serial operation mode register (csim31) notes: 1. when csie31 = 0 (sio31 operation stop status), the pins connected to si31 and so31 can be used for port functions. 2. when mode31 = 1 (receive mode), pin p94 can be used for port function. <7>6543210r/waddress after reset csim31 csie31 0 0 0 0 mode31 scl311 scl310 r/w ffaah 00h csie31 enable/disable specification for sio31 shift register operation serial counter port note 1 0 operation stop clear port function 1 operation enable count operation enable serial operation + port function mode31 transfer operation modes and flags operation mode transfer start trigger so31/sio31/p94 0 transmit/receive mode write to sio31 so31 output 1 receive-only mode note 2 read from sio31 port function scl311 scl310 clock selection (f x = 8.00 mhz) 0 0 external clock input 01 tm50 10 f x /2 3 11 f x /2 7 209 chapter 14 serial interface sio31 user ? s manual u16504ee1v1ud00 (2) serial mode switch register (sioswi) this register is used to select the sio31's 3-wire mode or 2-wire mode data communication mode. sioswi is set by an 1-bit or 8-bit memory manipulation instruction. the reset input sets sioswi to 00h. figure 14-3: format of serial mode switch register (sioswi) the following operation modes and start trigger have to be set for the usage of the 3-wire mode or the 2-wire mode data communication mode. 76543210r/waddress after reset sioswi0000000sioswir/wffabh00h sioswi sio31 - serial mode switch 0 3-wire mode (reset) 12-wire mode table 14-3: operating modes and start trigger mode31 3-wire or 2-wire mode of sio31 (sioswi) operation mode flag operation mode start trigger port 94 port 93 0 2-wire mode transmit/receive mode sio31 write so31 port function 1 receive mode sio31 read si31 port function 0 3-wire mode transmit/receive mode sio31 write so31 si31 1 receive mode sio31 read port function si31 210 chapter 14 serial interface sio31 user ? s manual u16504ee1v1ud00 14.5 serial interface operations this section explains two modes of sio31. 14.5.1 operation stop mode this mode is used if the serial transfers are not performed to reduce power consumption. during the operation stop mode, the pins can be used as normal i/o ports as well. register settings the operation stop mode can be set via the serial operation mode register (csim31). csim31 can be set via 1-bit or 8-bit memory manipulation instructions. the reset input sets the value to 00h. figure 14-4: format of serial operation mode register (csim31) notes: 1. when csie31 = 0 (sio31 operation stop status), the pins si31, so31 and sck31 can be used for port functions. 2. when csie31 = 1 (sio31 operation enabled status), the si31 pin can be used as a port pin if only the send function is used, and the so31 pin can be used as a port pin if only the receive-only mode is used. <7>6543210r/waddress after reset csim31 csie31 0 0 0 0 mode31 scl311 scl310 r/w ffaah 00h csie31 sio31 operation enable/disable specification shift register operation serial counter port 0 operation stop clear port function note 1 1 operation enable count operation enable serial operation + port function note 2 211 chapter 14 serial interface sio31 user ? s manual u16504ee1v1ud00 14.5.2 three-wire serial i/o mode the three-wire serial i/o mode is useful when connecting a peripheral i/o device that includes a clock-synchronous serial interface, a display controller, etc. this mode executes the data transfer via three lines: a serial clock line (sck31 ), serial output line (so31), and serial input line (si31). (1) register settings the 3-wire serial i/o mode is set via serial operation mode register (csim31). csim31 can be set via 1-bit or 8-bit memory manipulation instructions. the reset input set the value to 00h. figure 14-5: format of serial operation mode register (csim31) notes: 1. when csie31 = 0 (sio31 operation stop status), the pins si31, so31 and sck31 can be used for port functions. 2. when csie31 = 1 (sio31 operation enabled status), the si31 pin can be used as a port pin if only the send function is used, and the so31 pin can be used as a port pin if only the receive-only mode is used. caution: in the 3-wire serial i/o mode, set the port mode register (pm9) as required. set the output latch of the port to 0. <7>6543210r/waddress after reset csim31 csie31 0 0 0 0 mode31 scl311 scl310 r/w ffaah 00h csie31 enable/disable specification for sio31 shift register operation serial counter port 0 operation stop clear port function note 1 1 operation enable count operation enable serial operation + port function note 2 mode31 transfer operation modes and flags operation mode transfer start trigger so31 output 0 transmit/transmit and receive mode write to sio31 normal output 1 receive-only mode read from sio31 fixed a low level scl311 scl310 clock selection 0 0 external clock input to sck31 01 tm50 10 f x /2 3 11 f x /2 7 212 chapter 14 serial interface sio31 user ? s manual u16504ee1v1ud00 213 chapter 14 serial interface sio31 user ? s manual u16504ee1v1ud00 14.5.3 two-wire serial i/o mode the 2-wire serial i/o mode is useful when connecting a peripheral i/o device that includes a clock-syn- chronous serial interface, a display controller, etc. this mode executes the data transfer via two lines: a serial clock line (sck31), serial output line (so31), and serial input/output line (sio31). (1) register settings the 2-wire serial i/o mode is set via serial operation mode register 31 (csim31). csim31 can be set by an 1-bit or 8-bit memory manipulation instructions. the reset input sets csim31 to 00h. figure 14-7: format of serial operation mode register (csim31) note: when csie31 = 0 (sio31 operation stop status), the pins si31, so31 and sck31 can be used for port functions. caution: in the 2-wire serial i/o mode, set the port mode register (pm9) as required. set the output latch of the port to 0. <76543210r/waddress after reset csim31 csie31 0 0 0 0 mode31 scl311 scl310 r/w ffaah 00h csie31 enable/disable specification for sio31 shift register operation serial counter port 0 operation stop clear port function note 1 1 operation enable count operation enable serial operation + port function mode31 transfer operation modes and flags operation mode transfer start trigger so31 output 0 transmit/transmit and receive mode write to sio31 sio31 1 receive-only mode read from sio31 si31 scl311 scl310 clock selection 0 0 external clock input to sck31 01 tm50 10 f x /2 3 11 f x /2 7 214 chapter 14 serial interface sio31 user ? s manual u16504ee1v1ud00 215 chapter 14 serial interface sio31 user ? s manual u16504ee1v1ud00 (3) 3-wire communication operations in the three-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is sent or received synchronized with the serial clock. the serial i/o shift register (sio31) is shifted synchronized with the falling edge of the serial clock. the transmission data is held in the so31 latch and is transmitted from the so31 pin. the data is received via the si31 pin synchronized with the rising edge of the serial clock is latched to sio31. the completion of an 8-bit transfer automatically stops operation of sio31 and sets a serial trans- fer completion flag. figure 14-9: timing of three-wire serial i/o mode (4) 2-wire communication operations in the two-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is sent or received synchronized with the serial clock. the serial i/o shift register 31 (sio31) is shifted synchronized with the falling edge of the serial clock. the transmission data is held in the sio31 latch and is transmitted from the sio31 pin. the data is received via the sio31 pin synchronized with the rising edge of the serial clock is latched to sio31. the completion of an 8-bit transfer automatically stops operation of sio31 and sets interrupt request flag. figure 14-10: timing of two-wire serial i/o mode si31 di7 di6 di5 di4 di3 di2 di1 di0 serial transfer completion flag sck31 1 so31 do7 do6 do5 do4 do3 do2 do1 do0 2345678 transfer completion transfer starts in synchronized with the serial clock ? s falling edge data input sio31 di7 di6 di5 di4 di3 di2 di1 di0 serial transfer completion flag sck31 1 data output sio31 do7 do6 do5 do4 do3 do2 do1 do0 2345678 transfer completion transfer starts in synchronized with the serial clock ? s falling edge 216 chapter 14 serial interface sio31 user ? s manual u16504ee1v1ud00 (5) transfer start a serial transfer starts when the following conditions have been satisfied and transfer data has been set to serial i/o shift register 31 (sio31). the sio31 operation control bit must be set (csie = 1) in transmit/receive mode when csie31 = 1 and mode31 = 0, transfer starts when writing to sio31. in receive-only mode when csie31 = 1 and mode31 = 1, transfer starts when reading from sio31. caution: after the data has been written to sio31, the transfer will not start even if the csie31 bit value is set to ? 1 ? . the completion of an 8-bit transfer automatically stops the serial transfer operation and sets a serial transfer completion flag. after an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. 217 user ? s manual u16504ee1v1ud00 chapter 15 serial interface channel uart 15.1 uart functions the serial interface uart has the following modes. (1) operation stop mode this mode is used if the serial transfer is performed to reduce power consumption. for details, see 16.5.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode enables the full-duplex operation where one byte of data is transmitted and received after the start bit. the on-chip dedicated uart baud rate generator enables communications using a wide range of selectable baud rates. for details, see 16.5.2 asynchronous serial interface (uart) mode . figure 14-1 shows a block diagram of the uart macro. figure 15-1: block diagram of uart internal bus receive buffer rxb0 rxd/p62 txd/p63 receive shift register pe0 fe0 asis0 txs0 intst0 baud rate generator txe0 rxe0 ps01 ps00 cl0 sl0 asim0 intsr0 receive control parity check transmit shift register transmit control parity addition rxs0 intser0 x f /2 - x f /2 8 ove0 isrm0 218 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 15.2 uart configuration the uart includes the following hardware. (1) transmit shift register 1 (txs0) this register is for setting the transmit data. the data is written to txs0 for transmission as serial data. when the data length is set as 7 bits, bits 0 to 6 of the data written to txs0 are transmitted as serial data. writing data to txs0 starts the transmit operation. txs0 can be written via 8-bit memory manipulation instructions. it cannot be read. when reset is input, its value is ffh. cautions: 1. do not write to txs0 during a transmit operation. 2. the same address is assigned to txs0 and the receive buffer register (rxb0). a read operation reads values from rxb0. (2) receive shift register 1 (rxs0) this register converts serial data input via the rxd pin to parallel data. when one byte of the data is received at this register, the receive data is transferred to the receive buffer register (rxb0). rxs0 cannot be manipulated directly by a program. (3) receive buffer register (rxb0) this register is used to hold receive data. when one byte of data is received, one byte of new receive data is transferred from the receive shift register (rxs0). when the data length is set as 7 bits, receive data is sent to bits 0 to 6 of rxb0. the msb must be set to ? 0 ? in rxb0. rxb0 can be read to via 8-bit memory manipulation instructions. it cannot be written to. when reset is input, its value is ffh. caution: the same address is assigned to rxb0 and the transmit shift register (txs0). during a write operation, values are written to txs0. table 15-1: configuration of uart item configuration registers transmit shift register 1 (txs0) receive shift register 1 (rxs0) receive buffer register (rxb0) control registers asynchronous serial interface mode register (asim0) asynchronous serial interface status register (asis0) baud rate generator control register (brgc0) 219 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 (4) transmission control circuit the transmission control circuit controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to the transmit shift register (txs0), based on the values set to the asynchronous serial interface mode register (asim0). (5) reception control circuit the reception control circuit controls the receive operations based on the values set to the asyn- chronous serial interface mode register (asim0). during a receive operation, it performs error checking, such as parity errors, and sets various values to the asynchronous serial interface sta- tus register (asis0) according to the type of error that is detected. 15.3 list of sfrs (special function registers) table 15-2: list of sfrs (special function registers) sfr name symbol r/w units available for bit manipu- lation value when reset 1-bit 8-bit 16-bit transmit shift register txs0 w - 220 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 15.4 serial interface control registers the uart uses the following three types of registers for control functions. asynchronous serial interface mode register (asim0) asynchronous serial interface status register (asis0) baud rate generator control register (brgc0) (1) asynchronous serial interface mode register (asim0) this is an 8-bit register that controls the uart serial transfer operation. asim0 can be set by 1-bit or 8-bit memory manipulation instructions. reset input sets the value to 00h. figure 14-2 shows the format of asim0. figure 15-2: format of asynchronous serial interface mode register (asim0) (1/2) <7><6>543210r/waddress after reset asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 0 r/w ffa0h 00h txe0 rxe0 operation mode rxd0/p62 pin function txd0/p63 pin function 0 0 operation stop port function port function 01 uart0 mode (receive only) serial operation port function 10 uart0 mode (transmit only) port function serial operation 11 uart0 mode (transmit and receive) serial operation serial operation ps01 ps00 parity bit specification 00no parity 01 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl0 character length specification 0 7 bits 1 8 bits 221 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 figure 15-2: format of asynchronous serial interface mode register (asim0) (2/2) caution: do not switch the operation mode until the current serial transmit/receive operation has stopped. sl0 stop bit length specification for transmit data 01 bit 1 2 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs 222 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 (2) asynchronous serial interface status register (asis0) when a receive error occurs during uart mode, this register indicates the type of error. asis0 can be read using an 8-bit memory manipulation instruction. when reset is input, its value is 00h. figure 15-3: format of asynchronous serial interface status register (asis0) notes: 1. even if a stop bit length of two bits has been set to bit 2 (sl0) in the asynchronous serial interface mode register (asim0), the stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of the receive buffer register (rxb0) when an overrun error has occurred. until the contents of rxb0 are read, further overrun errors will occur when receiving data. 76543210r/waddress after reset asis0 0 0 0 0 0 pe0 fe0 ove0 r ffa1h 00h pe0 parity error flag 0 no parity error 1 parity error (incorrect parity bit detected) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) fe0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) 223 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 (3) baud rate generator control register (brgc0) this register sets the serial clock for uart. brgc0 can be set via an 8-bit memory manipulation instruction. when reset is input, its value is 00h. figure 14-4 shows the format of brgc0. figure 15-4: format of baud rate generator control register (brgc0) (1/2) (f x = 8.00 mhz) 76543210r/waddress after reset brgc0 0 tps02 tps01 tps00 mdl03 mdl02 mdl01 mdl00 r/w ffa2h 00h tps02 tps01 tps00 source clock selection for 5-bit counter n 000 f x /2 1 1 001 f x /2 2 2 010 f x /2 3 3 011 f x /2 4 4 100 f x /2 5 5 101 f x /2 6 6 110 f x /2 7 7 111 f x /2 8 8 224 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 figure 15-4: format of baud rate generator control register (brgc0) (2/2) caution: writing to brgc0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. there- fore, do not write to brgc0 during a communication operation. remarks: 1. f sck : source clock for 5-bit counter 2. n: value set via tps00 to tps02 (1 225 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 15.5 serial interface operations this section explains the different modes of the uart. 15.5.1 operation stop mode this mode is used when serial transfer is performed to reduce power consumption. in the operation stop mode, pins can be used as ordinary ports. register settings operation stop mode settings are made via the asynchronous serial interface mode register (asim0). txe0 and rxe0 must be set to 0. figure 15-5: register settings caution: do not switch the operation mode until the current serial transmit/receive operation has stopped. <7><6>543210r/waddress after reset asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 0 r/w ffa0h 00h txe0 rxe0 operation mode rxd0/p62 pin function txd0/p63 pin function 0 0 operation stop port function port function 01 uart0 mode (receive only) serial operation port function 10 uart0 mode (transmit only) port function serial operation 11 uart0 mode (transmit and receive) serial operation serial operation 226 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 15.5.2 asynchronous serial interface (uart) mode this mode enables full-duplex operation where one byte of the data is transmitted or received after the start bit. the on-chip dedicated uart baud rate generator enables communications by using a wide range of selectable baud rates. (1) register settings the uart mode settings are made via the asynchronous serial interface mode register (asim0), asynchronous serial interface status register (asis0), and the baud rate generator control register (brgc0). (a) asynchronous serial interface mode register (asim0) asim0 can be set by 1-bit or 8-bit memory manipulation instructions. when reset is input, its value is 00h. figure 15-6: format of asynchronous serial interface mode register (asim0) (1/2) <7><6>543210r/waddress after reset asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 0 r/w ffa0h 00h txe0 rxe0 operation mode rxd0/p62 pin function txd0/p63 pin function 0 0 operation stop port function port function 01 uart0 mode (receive only) serial operation port function 10 uart0 mode (transmit only) port function serial operation 11 uart0 mode (transmit and receive) serial operation serial operation ps01 ps00 parity bit specification 00no parity 01 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl0 character length specification 0 7 bits 1 8 bits 227 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 figure 15-6: format of asynchronous serial interface mode register (asim0) (2/2) caution: do not switch the operation mode until the current serial transmit/receive operation has stopped. sl0 stop bit length specification for transmit data 01 bit 1 2 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs 228 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 (b) asynchronous serial interface status register (asis0) asis0 can be read using an 8-bit memory manipulation instruction. when reset is input, its value is 00h. figure 15-7: format of asynchronous serial interface status register (asis0) notes: 1. even if a stop bit length of two bits has been set to bit 2 (sl0) in the asynchronous serial interface mode register (asim0), the stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of the receive buffer register (rxb0) when an overrun error has occurred. until the contents of rxb0 are read, further overrun errors will occur when receiving data. 76543210r/waddress after reset asis0 0 0 0 0 0 pe0 fe0 ove0 r ffa1h 00h pe0 parity error flag 0 no parity error 1 parity error (incorrect parity bit detected) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) 229 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 (c) baud rate generator control register (brgc0) brgc0 can be set via an 8-bit memory manipulation instruction. when reset is input, its value is 00h. figure 15-8: format of baud rate generator control register (brgc0) (1/2) (f x = 8.00 mhz) 76543210r/waddress after reset brgc0 0 tps02 tps01 tps00 mdl03 mdl02 mdl01 mdl00 r/w ffa2h 00h tps02 tps01 tps00 source clock selection for 5-bit counter n 000 f x /2 1 1 001 f x /2 2 2 010 f x /2 3 3 011 f x /2 4 4 100 f x /2 5 5 101 f x /2 6 6 110 f x /2 7 7 111 f x /2 8 8 230 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 figure 15-8: format of baud rate generator control register (brgc0) (2/2) caution: writing to brgc0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. there- fore, do not write to brgc0 during a communication operation. remarks: 1. f sck : source clock for 5-bit counter 2. n: value set via tps00 to tps02 (1 231 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 the transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. baud rate setting the main system clock is divided to generate the transmit/receive clock. the baud rate generated by the main system clock is determined according to the following formula. f x : oscillation frequency of main system clock in mhz n : value set via tps00 to tps02 (1 ? s source clock assigned to bits 4 to 6 (tps00 to tps02) of brgc0 and the ? n ? value in the above formula is shown in figure 15-4, ? format of baud rate generator control register (brgc0) (1/2), ? on page 223. remark: f x : oscillation frequency of main system clock. table 15-3: relation between 5-bit counter?s source clock and ?n? value tps02 tps01 tps00 source clock selection for 5-bit counter n 000 f x /2 1 1 001 f x /2 2 2 010 f x /2 3 3 011 f x /2 4 4 100 f x /2 5 5 101 f x /2 6 6 110 f x /2 7 7 111 f x /2 8 8 [baud rate] = f x 2 n+1 (k + 16) [kbps] 232 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 error tolerance range for baud rates the tolerance range for baud rates depends on the number of bits per frame and the counter ? s division rate [1/(16 + k)]. table 15-4 describes the relation between the main system clock and the baud rate and figure 14-9 shows an example of a baud rate error tolerance range. remarks: 1. f x : oscillation frequency of main system clock 2. n: value set via tps00 to tps02 (1 figure 15-9: error tolerance (when k = 0), including sampling errors remark: t: 5-bit counter ? s source clock cycle table 15-4: relation between main system clock and baud rate baud rate (bps) f x = 8.386 mhz f x = 8.000 mhz f x = 5.000 mhz f x = 4.1943 mhz brgco err (%) brgco err (%) brgco err (%) brgco err (%) 600 7bh 1.10 7ah 0.16 70h 1.73 6bh 1.14 1200 6bh 1.10 6ah 0.16 60h 1.73 5bh 1.14 2400 5bh 1.10 5ah 0.16 50h 1.73 4bh 1.14 4800 4bh 1.10 4ah 0.16 40h 1.73 3bh 1.14 9600 3bh 1.10 3ah 0.16 30h 1.73 2bh 1.14 19200 2bh -1.3 2ah 0.16 20h 1.73 1bh 1.14 31250 21h 1.10 20h 0 14h 0 11h -1.31 38400 1bh 1.10 1ah 0.16 10h 1.73 0bh 1.14 76800 0bh 1.10 0ah 0.16 00h 1.73 - - 11520002h1.0301h0.16---- basic timing (clock cycle t) start d0 d7 p stop high-speed clock (clock cycle t ? ) enabling normal reception start d0 d7 p stop low-speed clock (clock cycle t ? ) enabling normal reception start d0 d7 p stop 32t 64t 256t 288t 320t 352t ideal sampling point 304t 336t 30.45t 60.9t 304.5t 15.5t 15.5t 0.5t sampling error 33.55t 67.1t 301.95t 335.5t baud rate error tolerance (when k = 0) = = 4.8438 (%) 15.5 233 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 (2) communication operations (a) data format as shown in figure 15-10, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. the asynchronous serial interface mode register (asim0) is used to set the character bit length, parity selection, and stop bit length within each data frame. figure 15-10: format of transmit/receive data in asynchronous serial interface start bit............. 1 bit character bits... 7 bits or 8 bits parity bit........... even parity, odd parity, zero parity, or no parity stop bit(s)........ 1 bit or 2 bits when ? 7 bits ? is selected as the number of character bits, only the low-order 7 bits (bits 0 to 6) are valid. in this case during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to ? 0 ? . the asynchronous serial interface mode register (asim0) and the baud rate generator control register (brgc0) are used to set the serial transfer rate. if a receive error occurs, information about the receive error can be recognized by reading the asynchronous serial interface status register (asis0). d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame 234 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 (b) parity types and operations the parity bit is used to detect bit errors in transfer data. usually, the same type of parity bit is used by the transmitting and receiving sides. when odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected. when zero parity or no parity is set, errors are not detected. even parity during transmission the number of bits in transmit data that includes a parity bit is controlled so that there are an even number of ? 1 ? bits. the value of the parity bit is as follows. if the transmit data contains an odd number of ? 1 ? bits: the parity bit value is ? 1 ? . if the transmit data contains an even number of ? 1 ? bits: the parity bit value is ? 0 ? during reception the number of ? 1 ? bits is counted among the transfer data that include a parity bit, and a parity error occurs when the result is an odd number. odd parity during transmission the number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of ? 1 ? bits. the value of the parity bit is as follows. if the transmit data contains an odd number of ? 1 ? bits: the parity bit value is ? 0 ? if the transmit data contains an even number of ? 1 ? bits: the parity bit value is ? 1 ? during reception the number of ? 1 ? bits is counted among the transfer data that include a parity bit, and a parity error occurs when the result is an even number. zero parity during transmission, the parity bit is set to ? 0 ? regardless of the transmit data. during reception, the parity bit is not checked. therefore, no parity errors will occur regardless of whether the parity bit is a ? 0 ? or a ? 1 ? . no parity no parity bit is added to the transmit data. during reception, receive data is regarded as having no parity bit. since there is no parity bit, no parity errors will occur. 235 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 (c) transmission the transmit operation is started when transmit data is written to the transmit shift register (txs0). a start bit, parity bit, and stop bit(s) are automatically added to the data. starting the transmit operation shifts out the data in txs0, thereby emptying txs0, after which a transmit completion interrupt (intst0) is issued. the timing of the transmit completion interrupt is shown in figure 15-11. figure 15-11: timing of asynchronous serial interface transmit completion interrupt caution: do not write to the asynchronous serial interface mode register (asim0) during a transmit operation. writing to asim0 during a transmit operation may disable further transmit operations (in such cases, enter a reset to restore normal operation). whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt (intst0) or the interrupt request flag (stif) that is set by intst0. txd (output) d0 d1 d2 d6 d7 parity stop start intst0 (1) stop bit length: 1 bit txd (output) d0 d1 d2 d6 d7 parity start intst0 (2) stop bit length: 2 bits stop 236 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 (d) reception the receive operation is enabled when bit 6 (rxe0) of the asynchronous serial interface mode register (asim0) is set to "1", and input data via rxd pin is sampled. the serial clock specified by asim0 is used when sampling the rxd pin. when the rxd pin goes low, the 5-bit counter begins counting, the start timing signal for data sampling is output if half of the specified baud rate time has elapsed. if the sampling of the rxd0 pin input of this start timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and starts counting and data sampling begins. after the start bit is recog- nized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. once the reception of one data frame is completed, the receive data in the shift register is trans- ferred to the receive buffer register (rxb0) and a receive completion interrupt (intsr0) occurs. even if an error has occurred, the receive data in which the error occurred is still transferred to rxb0 and intsr0 occurs (see figure 14-9). if the rxe0 bit is reset (to ? 0 ? ) during a receive operation, the receive operation is stopped imme- diately. at this time, neither the contents of rxb0 and asis0 will change, nor does intsr0 or intser0 occur. figure 15-12 shows the timing of the asynchronous serial interface receive completion interrupt. figure 15-12: timing of asynchronous serial interface receive completion interrupt caution: be sure to read the contents of the receive buffer register (rxb0) even when a receive error has occurred. overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb0 are read. rxd (input) d0 d1 d2 d6 d7 parity stop start intsr0 237 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 (e) receive errors three types of errors can occur during a receive operation: parity error, framing error, or overrun error. if, as the result of the data reception, an error flag is set to the asynchronous serial interface status register (asis0), a receive error interrupt (intser0) will occur. receive error interrupts are generated before receive interrupts (intsr0). table 15-5 lists the causes of receive errors. as part of the receive error interrupt (intser0) servicing, the contents of asis0 can be read to determine which type of error occurred during the receive operation (see table 14-5 and figure 15-13). the content of asis0 is reset (to ? 0 ? ) if the receive buffer register (rxb0) is read or when the next data is received (if the next data contains an error, another error flag will be set). figure 15-13: receive error timing cautions: 1. the contents of asis0 are reset (to ? 0 ? ) when the receive buffer register (rxb0) is read or when the next data is received. to obtain information about the error, be sure to read the contents of asis0 before reading rxb0. 2. be sure to read the contents of the receive buffer register (rxb0) even when a receive error has occurred. overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb0 are read. table 15-5: causes of receive errors receive error cause asis0 value parity error parity specified during transmission does not match parity of receive data 04h framing error stop bit was not detected 02h overrun error reception of the next data was completed before data was read from the receive buffer register 01h rxd0 (input) d0 d1 d2 d6 d7 parity stop start intsr0 intser0 intser0 (when parity error occurs) 238 chapter 15 serial interface channel uart user ? s manual u16504ee1v1ud00 15.6 behavior of uart during standby of the controller serial transfer operations can be performed during halt mode of the controller. during stop mode, serial transfer operations are stopped and the values in the asynchronous serial interface mode register (asim0), the transmit shift register (txs0), the receive shift register (rxs0), and the receive buffer register (rxb0) remain as they were just before the clock was stopped. output from the txd pin retains the current data if the clock is stopped (if the system enters stop mode) during a transmit operation. if the clock is stopped during a receive operation, the data received before the clock was stopped is retained and all subsequent operations are stopped. the receive operation can be restarted once the clock is restarted. 239 user ? s manual u16504ee1v1ud00 chapter 16 can controller table 16-1: outline of the function feature details protocol can2.0 with active extended frame capability (bosch specification 2.0 part b) baudrate max. 500 kbps at 8 mhz clock supply bus line control cmos in / out for external transceiver clock selected by register data storage cpu ram area with shared access dcan uses up to 288 byte of ram unused bytes can be used by cpu for other tasks message organisation received messages will be stored in ram area depending on message identifier transmit messages have two dedicated buffers in ram area message number one input receive shadow buffer (not readable by user) up to 16 receive message objects including 2 masks two transmit channels message sorting unique identifier on all 16 receive message objects up to 2 message objects with mask global mask for all messages dcan protocol sfr access for general control interrupt transmit interrupt for each channel one receive interrupt with enable control for each message one error interrupt time functions support of time stamp and global time system programmable single shot mode diagnostic readable error counters ? valid protocol activity flag ? for verification of bus connection ? receive only ? mode for automatic baudrate detection power down modes sleep mode: wake up from can bus stop mode: no wake-up from can bus 240 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.1 can protocol can is an abbreviation of "c ontroller a rea n etwork", and is a class c high speed multiplexed communi- cation protocol. can is specified by bosch in the can specification 2.0 from september 1991 and is standardized in iso-11898 (international organization for standardization) and sae (society of auto- motive engineers). 16.1.1 protocol mode function (1) standard format mode this mode supports an 11-bit message identifier thus making it possible to differentiate between 2048 types of messages. (2) extended format mode in the extended format mode, the identifier has 29 bits. it is built by the standard identifier (11 bits) and an extended identifier (18 bits). when the ide bits of the arbitration field is "recessive", the frame is sent in the extended format mode. when a message in extended format mode and a remote frame in standard format mode are simultaneously transmitted, the node transmitting the message with the standard mode wins the arbitration. (3) bus values the bus can have one of two complementary logical values: "dominant" or "recessive". during simultaneous transmission of "dominant" and "recessive" bits, the resulting bus value will be "dominant" (non destructive arbitration). for example, in case of a wired-and implementation of the bus, the "dominant" level would be represented by a logical "0" and the "recessive" level by a logical ? 1 ? . this specific representation is used in this manual. physical states (e.g. electrical voltage, light) that represent the logical levels are not given in this document. 16.1.2 message format the can protocol message supports different types of frames. the types of frames are listed below: data frame: carries the data from a transmitter to the receiver. remote frame: transmission demand frame from the requesting node. error frame: frame sent on error detection. overload frame: frame sent when a data or remote frame would be overwritten by the next one before the receiving node could process it. the reception side did not finish its operations on the reception of the previously received frame yet. 241 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.1.3 data frame / remote frame figure 16-1: data frame figure 16-2: remote frame remark: this frame is transmitted when the reception node requests transmission. data field is not transmitted even if the data length code '0' in the control field. ? bus idle ?? ? ?? ? ? ?? ( ) ( ) ( ) interframe space end of frame ack field crc field data field control field arbitration field start of frame data frame r d 1 (11 + 1) (29 + 3) 6 0 ... 64 16 2 73 ? ??? ?? ? ? ? ( ) ( ) ( ) bus idle interframe space end of frame ack field crc field control field arbitration field start of frame remote frame r d 242 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.1.4 description of each field (1) "r" indicates recessive level. "d" indicates dominant level. start of frame: the start of data frame and remote frame are indicated. figure 16-3: data frame the start of frame (sof) is denoted by the falling edge of the bus signal. reception continues when 'dominant level' is detected at the sample point. the bus becomes idle state when 'recessive level' is detected at a sample point. (2) arbitration field: sets priority, specifies data frame or remote frame, and defines the protocol mode. figure 16-4: arbitration field/standard format mode start of frame r d 1 bit interframe space on bus idle arbitration field rtr (1 bit) control field arbitration field ide (1 bit) r0 identifier id28 . . . id18 (11 bits) r d 243 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-5: arbitration field/extended format mode id28 - id0 is the identifier. the identifier is transmitted with msb at first position. substitute remote request (srr) is only used in extended format mode and is always recessive. table 16-2: bit number of the identifier table 16-3: rtr setting table 16-4: mode setting protocol mode identifier number standard format mode 11 bits extended format mode 29 bits frame type rtr bit data frame 0 remote frame 1 protocol mode ide bit standard format mode 0 extended format mode 1 srr (1 bit) control field arbitra tion field ide (1 bit) r0 identifier id28 . . . id18 (11 bits) identifier id17 . . . id0 (18 bits) rtr (1 bit) r1 r d 244 chapter 16 can controller user ? s manual u16504ee1v1ud00 (3) control field: the data byte number dlc in the data field specifies the number of data bytes in the current frame (dlc=0 to 8). figure 16-6: control field (standard format mode) figure 16-7: control field (extended format mode) the bits r0 and r1 are reserved bits for future use and are recommended to be recessive. table 16-5: data length code setting remark: in case of a remote frame, the data field is not generated even if data length code '0'. data length code dlc3 dlc2 dlc1 dlc0 number of data bytes 0000 0 0001 1 .... .... 245 chapter 16 can controller user ? s manual u16504ee1v1ud00 (4) data field: this field carries the data bytes to be sent. the number of data bytes is defined by the dlc value. figure 16-8: data field (5) crc field: this field consists of a 15-bit crc sequence to check the transmission error and a crc delimiter. figure 16-9: crc field 15 bits crc generation polynomial is expressed by p(x) = x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1. transmission node: transmits the crc sequence calculated from the start of frame, arbitration field, control field and data field eliminating stuff bits. reception node: the crc received will be compared with the crc calculated in the receiving node. for this calculation the stuff bits of the received crc are eliminated. in case these do not match, the node issues an error frame. data (8 bits) data field control field crc field r d data (8 bits) crc sequence (15 bits) crc field data field and control field ack field r d crc delimiter (1 bit) 246 chapter 16 can controller user ? s manual u16504ee1v1ud00 (6) ack field: for check of normal reception. figure 16-10: ack field receive node sets the ack slot to dominant level if no error was detected. (7) end of frame: indicates the end of the transmission/reception. figure 16-11: end of frame ack slot (1 bit) ack field crc field end of frame r d ack delimiter (1 bit) (7 bits) end of frame ack field interframe space of overload frame r d 247 chapter 16 can controller user ? s manual u16504ee1v1ud00 (8) interframe space: this sequence is inserted after data frames, remote frames, error frames, and overload frames in the serial bitstream on the bus to indicate start or end of a frame. the length of the interframe space depends on the error state (active or passive) of the node. (a) error active: consists of 3 bits intermission and bus idle. figure 16-12: interframe space/error active (b) error passive: consists of 3 bits intermission, suspend transmission and bus idle. figure 16-13: interframe space/error passive remark: the nominal value of the intermission field is 3 bits. however, transmission nodes may start immediately a transmission already in the 3 rd bit of this field when a dominant level is detected. table 16-6: operation in the error state error state operation error active any node in this state is able to start a transmission whenever the bus is idle. error passive any node in this state has to wait for 11 consecutive recessive bits before initiating a transmission. intermission (3 bits) interframe space any frame any frame r d bus idle (0 to bits) suspend transmission (8 bits) interframe space each frame each frame r d bus idle intermission (3 bits) (0 to bits) 248 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.1.5 error frame this frame is sent from a node if an error is detected. the type of an error frame is defined by its error flag: active error flag or passive error flag. which kind of flag a node transmits after detecting an error condition depends on the internal count of the error counters of each node. figure 16-14: error frame table 16-7: definition of each field no. name bit number definition 1 error flag 6 error active node: sends 6 bits dominant level continuously. error passive node: sends 6 bits recessive level continuously. 2 error flag superpositioning 0 to 6 nodes receiving an ? error flag ? detect bit stuff errors and issue error flags ? themselves. 3 error delimiter 8 sends 8 bits recessive level continuously. in case of monitoring dominant level at 8th bit, an overload frame is transmitted after the next bit. 4 erroneous bit - an error frame is transmitted continuously after the bit where the error has occurred (in case of a crc error, transmission continues after the ack delimiter). 5 interframe space/ overload frame 3/14 20 max interframe space or overload frame continues. ?? ? ? ? ( ) ( ) error frame interframe space or overload frame error delimiter error flag error bit r d error flag 249 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.1.6 overload frame this frame is started at the first bit of the intermission when the reception node is busy with exploiting the receive operation and is not ready for further reception. when a bit error is detected in the intermission, also an overload frame is sent following the next bit after the bit error detection. detecting a dominant bit during the 3 rd bit of intermission will be interpreted as start of frame. at most two overload frames may be generated to delay the next data frame or remote frame. figure 16-15: overload frame table 16-8: definition of each frame no. name bit number definition 1 overload flag 6 sent 6 bits dominant level continuously. 2 overload flag from any node 0 to 6 a node that receives an overload flag in the interframe space. issues an overload flag. 3 overload delimiter 8 sends 8 bits recessive level continuously. in case of monitoring dominant level at 8th bit, an overload frame is transmitted after the next bit. 4 any frame - output following the end of frame, error delimiter and overload delimiter. 5 interframe space/ overload frame 3/14 20 max interframe space or overload frame continues. ?? ? ? ? ( ) ( ) overload frame interframe space or overload frame overload delimiter overload flag superpositioning (node n) overload flag (node m) each frame r d 250 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.2 function 16.2.1 arbitration if two or more nodes happen to start transmission in coincidence, the access conflict is solved by a bit- wise arbitration mechanism during transmission of the arbitration field. (1) when a node starts transmission: during bus idle, the node having the output data can transmit. (2) when more than one node starts transmission: the node with the lower identifier wins the arbitration. any transmitting node compares its output arbitration field and the data level on the bus. it looses arbitration, when it sends recessive level and reads dominant from bus. table 16-9: arbitration (3) priority of data frame and remote frame: when a data frame and remote frame with the same message identifier are on the bus, the data frame has priority because its rtr bit carries 'dominant level'. the data frame wins the arbitration. 16.2.2 bit stuffing when the same level continues for more than 5 bits, bit stuffing (insert 1 bit with inverse level) takes place. due to this a resynchronization of the bit timing can be done at least every 10 bits. nodes detecting an error condition send an error frame, violating the bit stuff rule and indicating this message to be erroneous for all nodes. table 16-10: bit stuffing level detection status of arbitrating node conformity of level continuous transmission non-conformity of level the data output is stopped from the next bit and reception operation starts. transmission during the transmission of a data frame and a remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, 1 bit level with reverse level of data is inserted before the following bit. reception during the reception of a data frame and a remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, the reception is continued by deleting the next bit. 251 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.2.3 multi master as the bus priority is determined by the identifier, any node can be the bus master. 16.2.4 multi cast any message can be received by any node (broadcast). 16.2.5 sleep mode/stop function this is a function to put the can controller in waiting mode to achieve low power consumption. the sleep mode of the dcan complies to the method described in iso 11898. additional to this sleep mode, which can be woken up by bus activities, the stop mode is fully con- trolled by the cpu device. 252 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.2.6 error control function (1) error types table 16-11: error types (2) output timing of the error frame table 16-12: output timing of the error frame (3) measures when error occurs transmission node re-transmits the data frame or the remote frame after the error frame. the can standard (iso-11898) allows a programmable suppression of this re-transmission. it is called single shot mode. ty p e description of error detection state detection method detection condition transmission/ reception field/frame bit error comparison of output level and level on the bus (except stuff bit) disagreement of both levels transmission/ reception node bit that output data on the bus at the start of frame to the end of frame, error frame and overload frame. stuff error check of the reception data at the stuff bit 6 consecutive bits of the same output level transmission/ reception node start of frame to crc sequence crc error comparison of the crc generated from the reception data and the received crc sequence disagreement of crc reception node start of frame to data field form error field/frame check of the fixed format detection of the fixed for- mat error reception node crc delimiter ack field end of frame error frame overload frame ack error check of the ack slot by the transmission node detection of recessive level in ack slot transmission node ack slot type output timing bit error, stuff error, form error, ack error error frame is started at the next bit timing following the detected error error passive crc error error frame is started at the next bit timing following the ack delimiter 253 chapter 16 can controller user ? s manual u16504ee1v1ud00 (4) error state (a) types of error state three types of error state: these are error active, error passive and bus off. the transmission error counter (tec) and the reception error counter (rec) control the error state. the error counters are incremented on each error occurrence (refer to table 3-6). if the value of error counter exceeds 96, warning level for error passive state is reached. when only one node is active at start-up, it may not receive an acknowledgment on a transmitted message. this will increment tec until error passive state is reached. the bus off state will not be reached because for this specific condition tec will not increment any more if values greater than 127 are reached. a node in bus off state will not issue any dominant level on the can transmit pin. the reception of messages is not affected by the bus off state. table 16-13: types of error type operation value of error counter output error flag type error active transmission/ reception 0 to 127 active error flag (6 bits of dominant level continue) error passive transmission 128 to 255 passive error flag (6 bits of recessive level con- tinue) reception 128 or more bus off transmission more than 255 communication cannot be made reception - does not exist 254 chapter 16 can controller user ? s manual u16504ee1v1ud00 (b) error counter error counter counts up when an error has occurred, and counts down upon successful transmission and reception. the error counters are updated during the first bit of an error flag. table 16-14: error counter (c) overload frame in case the recessive level of first intermission bit is driven to dominant level, an overload frame occurs on the bus. upon detection of an overload frame any transmit request will be postponed until the bus becomes idle. state transmission error counter (tec) reception error counter (rec) reception node detects an error (except bit error in the active error flag or overload flag). no change +1 reception node detects dominant level following the error flag of the own error frame. no change +8 transmission node transmits an error flag. exception: 1. ack error is detected in the error passive state and domi- nant level is not detected in the passive error flag sent. 2. stuff error generation in arbitration field. +8 no change bit error detection during active error flag and overload flag when transmitting node is in error active state. +8 no change bit error detection during active error flag and overload flag when receiving node is in error active state. no change +8 when the node detects fourteen continuous dominant bits counted from the beginning of the active error flag or the over- load flag, and every time, eight subsequent dominant bits after that are detected. every time when the node detects eight continuous dominant bits after the passive error flag. +8 +8 when the transmitting node has completed to sent without error. -1 (-0 when error counter = 0) no change when the reception node has completed to receive without error. no change -1 (1 ? 0 (rec = 0) 119-127 (rec > 127) 255 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.2.7 baud rate control function (1) nominal bit time (8 to 25 time quanta) definition of 1 data bit time is as follows. figure 16-16: nominal bit time (8 to 25 time quanta) sync segment: in this segment the bit synchronization is performed. prop segment: this segment absorbs delays of the output buffer, the can bus and the input buffer. prop segment time = (output buffer delay) + (can bus delay) + (input buffer delay). phase segment 1/2: these segments compensate the data bit time error. the larger the size measured in tq is, the larger is the tolerable error. the synchronization jump width (sjw) specifies the synchronization range. the sjw is programmable. sjw can have less or equal number of tq as phase segment 2. table 16-15: segment name and segment length note: ipt = information processing time. it needs to be less than or equal to 2 tq. segment name segment length (allowed number of tqs) sync segment (synchronization segment) 1 prop segment (propagation segment) programmable 1 to 8 phase segment 1 (phase buffer segment 1) programmable 1 to 8 phase segment 2 (phase buffer segment 2) maximum of phase segment 1 and the ipt note sjw programmable 1 to 4 sync segment prop segment phase segment 1 phase segment 2 nominal bit time sjw sjw sample point [1 minimum time for one time/quantum (tq) = 1/fx] 256 chapter 16 can controller user ? s manual u16504ee1v1ud00 (2) adjusting synchronization of the data bit the transmission node transmits data synchronized to the transmission node bit timing. the reception node adjusts synchronization at recessive to dominant edges on the bus. depending on the protocol this synchronization can be a hard or soft synchronization. (a) hard synchronization this type of synchronization is performed when the reception node detects a start of frame in the bus idle state. when the node detects a falling edge of a sof, the current time quanta becomes the synchronization segment. the length of the following segments are defined by the values programmed into the sync0 and sync1 registers. figure 16-17: adjusting synchronization of the data bit sync segment prop segment phase segment 1 phase segment 2 can bus bit timing bus idle start of frame 257 chapter 16 can controller user ? s manual u16504ee1v1ud00 (b) soft synchronization when a recessive to dominant level change on the bus is detected, a soft synchronization is performed. if the phase error is larger than the programmed sjw value, the node will adjust the timing by applying this sjw-value. full synchronization is achieved by subsequent adjustments on the next recessive to dominant edge(s). these errors that are equal or less of the programmed sjw are corrected instantly and full synchronization is achieved already for the next bit. the tq at which the edge occurs becomes sync segment forcibly, if the phase error is less than or equal to sjw. figure 16-18: bit synchronization sync segment prop segment phase segment -sjw sync segment prop segment phase segment 2 +sjw 258 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.2.8 state shift chart figure 16-19: transmission state shift chart start of frame arbitration field data field control field crc field ack field end of frame intermission 1 error frame overload frame bus idle intermission 2 c a b initialization setting reception reception reception end rtr = 0 end end end end error active bit error rtr = 1 bit error bit error bit error ack error bit error bit error end end bit error form error error passive 8 bits of '1' start of frame reception start of frame transmission 259 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-20: reception state shift chart start of frame arbitration field data field control field crc field ack field end of frame intermission 1 error frame overload frame bus idle a c initialization setting transmission transmission b transmission end rtr = 0 end end end end rtr = 1 stuff error stuff error crc error, stuff error ack error, bit error bit error, form error bit error end end not ready form error start of frame transmission start of frame reception stuff error not ready 260 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-21: error state shift chart (a) transmission (b) reception error active bus off error passive tec > 128 tec > 256 tec < 127 tec = 0 tec = transmission error counter error active error passive rec > 128 rec = reception error counter rec < 127 261 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.3 outline description figure 16-22: structural block diagram this interface part handles all protocol activities by hardware in the can protocol part. the memory access engine fetches information for the can protocol transmission from the dedicated ram area to the can protocol part or compares and sorts incoming information and stores it into predefined ram areas. the dcan interfaces directly to the ram area that is accessible by the dcan and by the cpu. the dcan part works with an external bus transceiver which converts the transmit data and receive data lines to the electrical characteristics of the can bus itself. can protocol interface management (includes global registers) memory access engine cpu high speed ram receive messages memory buffer ram dcan-interface bus arbitration logic cpu access receive messages receive messages receive messages transmit buffers transmit buffers timer external transceiver canl canh sfr time stamp signal 262 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.4 connection with target system the dcan macro has to be connected to the can bus with an external transceiver. figure 16-23: connection to the can bus 16.5 can controller configuration the can-module consists of the following hardware . table 16-16: can configuration item configuration message definition in ram area can input/output 1 (ctxd) 1 (crxd) control registers can control register (canc) transmit control register (tcr) receive message register (rmes) redefinition control register (redef) can error status register (canes) transmit error counter (tec) receive error counter (rec) message count register (mcnt) bit rate prescaler (brprs) synchronous control register 0 (snyc0) synchronous control register 1 (sync1) mask control register (maskc) dcan macro transceiver ctxd crxd canl canh 263 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.6 special function register for can-module the following sfr bits can be accessed with 1-bit instructions. the other sfr registers have to be accessed with 8-bit instructions. table 16-17: sfr definitions register name symbol r/w bit manipulation units after reset 1-bit 8-bit 16-bit can control register canc r/w table 16-18: sfr bit definitions name description bit sofe start of frame enable canc.4 sleep sleep mode canc.2 init initialize canc.0 def redefinition enable redef.7 264 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.7 message and buffer configuration notes: 1. contents is undefined, because data resides in normal ram area. 2. this address is an offset to the ram area starting address defined with cadd0/1 in the message count register (mcnt). table 16-19: message and buffer configuration address note 2 register name r/w after reset 00xh transmit buffer 0 r/w note 1 01xh transmit buffer 1 02xh receive message 0 / mask 0 03xh receive message 1 04xh receive message 2 / mask 1 05xh receive message 3 06xh receive message 4 07xh receive message 5 08xh receive message 6 09xh receive message 7 0axh receive message 8 0bxh receive message 9 0cxh receive message 10 0dxh receive message 11 0exh receive message 12 0fxh receive message 13 10xh receive message 14 11xh receive message 15 265 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.8 transmit buffer structure the dcan has two independent transmit buffers. the two buffers have a 16 byte data structure for standard and extended frames with the ability to send up to 8 data bytes per message. the structure of the transmit buffer is similar to the structure of the receive buffers. the cpu can use addresses that are specified as ? unused ? in the transmit buffer layout. as well the cpu may use unused id addresses, unused data addresses note , and an unused transmit buffer of the dcan for its own purposes. the con- trol bits, the identification and the message data have to be stored in the message ram area. the transmission control is done by the tcr register. a transmission priority selection allows the cus- tomer to realize an application specific priority selection. after the priority selection the transmission can be started by setting the txrqn bit (n = 0, 1). in the case that both transmit buffers are used, the transmit priorities can be set. for this purpose the dcan has the txp bit in the tcr register. the application software has to set this priority before the transmission is started. the two transmit buffers supply two independent interrupt lines for an interrupt controller. note: message objects that need less than 8 data byte (dlc < 8) may use the remaining bytes (8 - dlc) for application purposes. 16.9 transmit message format note: this address is a relative offset to the starting address of the transmit buffer. table 16-20: transmit message format name address note bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcon n0h ide rtr 0 0 dlc3 dlc2 dlc1 dlc0 n1h unused idtx0 n2h id standard part idtx1 n3h id standard part 0 0 0 0 0 idtx2 n4h id extended part idtx3 n5h id extended part idtx4 n6h id extended part 0 0 0 0 0 0 n7h unused data0 n8h message data byte 0 data1 n9h message data byte 1 data2 nah message data byte 2 data3 nbh message data byte 3 data4 nch message data byte 4 data5 ndh message data byte 5 data6 neh message data byte 6 data7 nfh message data byte 7 266 chapter 16 can controller user ? s manual u16504ee1v1ud00 (1) transmit message definition the memory location labelled tcon includes the information of the rtr bit and the bits of the control field of a data or remote frame. tcon is set with a 1-bit or an 8-bit memory manipulation instruction. reset input sets tcon to an undefined value. figure 16-24: transmit message definition bits remark: the control field describes the format of frame that is generated and its length. the reserved bits of the can protocol are always sent in dominant state (0). note: the data length code selects the number of bytes which have to be transmitted. valid entries for the data length code (dlc) are 0 to 8. if a value greater than 8 is selected, 8 bytes are transmitted in the data frame. the data length code is specified in dlc3 through dlc0. symbol76543210addressafter resetr/w tcon ide rtr 0 0 dlc3 dlc2 dlc1 dlc0 xxx0h undefined r/w ide identifier extension select 0 transmit standard frame message; 11 bit identifier 1 transmit extended frame message; 29 bit identifier rtr remote transmission select 0 transmit data frames 1 transmit remote frames dlc3 dlc2 dlc1 dlc0 data length code selection of transmit message 0000 0 data bytes 0001 1 data bytes 0010 2 data bytes 0011 3 data bytes 0100 4 data bytes 0101 5 data bytes 0110 6 data bytes 0111 7 data bytes 1000 8 data bytes others than above note 267 chapter 16 can controller user ? s manual u16504ee1v1ud00 (2) transmit identifier definition these memory locations set the message identifier in the arbitration field of the can protocol. idtx0 to idtx4 register can be set with a 1-bit or an 8-bit memory manipulation instruction. reset input sets idtx0 to idtx4 to an undefined value. figure 16-25: transmit identifier remark: if a standard frame is defined by the ide bit in the tcon byte then idtx0 and idtx1 are used only. idtx2 to idtx4 are free for use by the cpu for application needs. symbol76543210addressafter resetr/w idtx0id28id27id26id25id24id23id22id21 xxx2hundefinedr/w idtx1id20id19id1800000xxx3hundefinedr/w idtx2id17id16id15id14id13id12id11id10 xxx4hundefinedr/w idtx3 id9 id8 id7 id6 id5 id4 id3 id2 xxx5h undefined r/w idtx4id1id0000000xxx6hundefinedr/w 268 chapter 16 can controller user ? s manual u16504ee1v1ud00 (3) transmit data definition these memory locations set the transmit message data of the data field in the can frame. data0 to data7 can be set with a 1-bit or an 8-bit memory manipulation instruction. reset input sets data0 to data7 to an undefined value. figure 16-26: transmit data remark: unused data bytes that are not used by the definition in the dlc bits in the tcon byte are free for use by the cpu for application needs. symbol76543210addressafter resetr/w data0 xxx8h undefined r/w data1 xxx9h undefined r/w data2 xxxah undefined r/w data3 xxxbh undefined r/w data4 xxxch undefined r/w data5 xxxdh undefined r/w data6 xxxeh undefined r/w data7 xxxfh undefined r/w 269 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.10 receive buffer structure the dcan has up to 16 receive buffers. the number of used buffers is defined by the mcnt register. unused receive buffers can be used as application ram for the cpu. the received data is stored directly in this ram area. the 16 buffers have a 16 byte data structure for standard and extended frames with a capacity of up to 8 data bytes per message. the structure of the receive buffer is similar to the structure of the transmit buffers. the semaphore bits dn and muc enable a secure reception detection and data handling. for the first 8 receive message buffers the successful reception is mirrored by the dn-flags in the rmes register. the receive interrupt request can be enabled or disabled for each used buffer separately. 270 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.11 receive message format notes: 1. this address is a relative offset to the start address of the receive buffer. 2. rtr rec is the received value of the rtr message bit when this buffer is used together with a mask function. by using the mask function a successfully received identifier overwrites the bytes idrec0 and idrec1 for standard frame format and idrec0 to idrec4 for extended frame format. for the rtr rec bit exist two modes: rtr bit in the mcon byte of the dedicated mask is set to 0. in this case rtr rec will always be written to 0 together with the update of the idn bits in idrec1. the received frame type (data or remote) is defined by the rtr bit in idcon of the buffer. rtr bit in the mcon byte of the dedicated mask is set to 1 (data and remote frames are accepted). in this case the rtr bit in idcon has no meaning. the received mes- sage type passed the mask is shown in rtr rec . if a buffer is not assigned to a mask function (mask 1, mask 2 or global mask) the bytes idrec0 to idrec4 are only read for comparing. during initialization the rtr rec should be defined to 0. table 16-21: receive message format name address note 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 idcon n0h 0 0 000enirtr ide dstat n1h dn muc r1 r0 dlc idrec0 n2h id standard part idrec1 n3h id standard part 0 0 0 0 rtr rec note 2 idrec2 n4h id extended part idrec3 n5h id extended part idrec4 n6h id extended part00000 0 n7h unused data0 n8h message data byte 0 data1 n9h message data byte 1 data2 nah message data byte 2 data3 nbh message data byte 3 data4 nch message data byte 4 data5 ndh message data byte 5 data6 neh message data byte 6 data7 nfh message data byte 7 271 chapter 16 can controller user ? s manual u16504ee1v1ud00 (1) receive control bits definition the memory location labelled idcon defines the kind of frame (data or remote frame with stand- ard or extended format) that is monitored for the associated buffer. notification by the receive inter- rupt upon successful reception can be selected for each receive buffer separately. idcon can be set with a 1-bit or an 8-bit memory manipulation instruction. reset input sets idcon to an undefined value. figure 16-27: control bits for receive identifier the control bits define the type of message that is transferred in the associated buffer if this type of message appears on the bus. this byte will never be written by the dcan. only the host cpu can change this byte. note: the user has to define with the eni bit if he wants to set a receive interrupt request when new data is received in this buffer. symbol76543210addressafter resetr/w idcon00000enirtridexxx0hundefinedr/w ide identifier extension select 0 receive standard frame message; 11-bit identifier 1 receive extended frame message; 29-bit identifier rtr remote transmission select 0 receive data frames 1 receive remote frames eni enable interrupt on receive note 0 no interrupt generated 1 generate receive interrupt after reception of valid message 272 chapter 16 can controller user ? s manual u16504ee1v1ud00 (2) receive status bits definition the memory location labelled dstat sets the receive status bits of the arbitration field of the can protocol. dstat can be set with a 1-bit or an 8-bit memory manipulation instruction. reset input sets dstat to an undefined value. figure 16-28: receive status bits (1/2) the receive status reflects the current status of a message. it signals whether new data is stored or if the dcan currently transfers data into this buffer. in addition the data length of the last transferred data and the reserved bits of the protocol are shown. the dcan-module sets dn twice. at first when it starts storing a message from the shadow buffer into the receive buffer and secondly when it finished the operation. the cpu needs to clear this bit, to signal by itself that it has read the data. during initialization of the receive buffers the dn-bit should also be cleared. otherwise the cpu gets no information on an update of the buffer after a successful reception. the dcan-module sets muc when it starts transferring a message into the buffer and clears the muc bit when the transfer is finished. symbol76543210addressafter resetr/w dstat dn muc r1 r0 dlc3 dlc2 dlc1 dlc0 xxx1h undefined r/w dn data new 0 no change in data 1 data changed muc memory update 0 can does not access data part 1 can is transferring new data to message buffer r1 reserved bit 1 0 reserved bit 1 of received message was ? 0 ? 1 reserved bit 1 of received message was ? 1 ? r0 reserved bit 0 0 reserved bit 0 of received message was ? 0 ? 1 reserved bit 0 of received message was ? 1 ? 273 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-28: receive status bits (2/2) dstat is written by the dcan two times during message storage: at the first access to this buffer dn = 1, muc = 1, reserved bits and dlc are written. at the last access to this buffer dn = 1, muc = 0, reserved bits and dlc are written. note: valid entries for the data length code are 0 to 8. if a value higher than 8 is received, 8 bytes are stored in the message buffer frame together with the data length code received in the dlc of the message. dlc3 dlc2 dlc1 dlc0 data length code selection of receive message 0 0 0 0 0 data bytes 0 0 0 1 1 data bytes 0 0 1 0 2 data bytes 0 0 1 1 3 data bytes 0 1 0 0 4 data bytes 0 1 0 1 5 data bytes 0 1 1 0 6 data bytes 0 1 1 1 7 data bytes 1 0 0 0 8 data bytes others than above note 274 chapter 16 can controller user ? s manual u16504ee1v1ud00 (3) receive identifier definition these memory locations define the receive identifier of the arbitration field of the can protocol. idrec0 to idrec4 can be set with a 1-bit or an 8-bit memory manipulation instruction. reset input sets idrec0 to idrec4 to an undefined value. figure 16-29: receive identifier the identifier of the receive message has to be defined during the initialization of the dcan. the dcan uses this data for the comparison with the identifiers received on the can bus. for normal message buffers without mask function this data is only read by the dcan for comparison. in combina- tion with a mask function this data is overwritten by the received id that has passed the mask. the identifier of the receive messages should not be changed without being in the initialization phase or setting the receive buffer to redefinition in the rdef register, because the change of the contents can happen at the same time when the dcan uses the data for comparison. this can cause inconsistent data stored in this buffer and also the id-part can be falsified in case of using mask function. remarks: 1. the unused parts of the identifier (idrec1 bit 4 - 0 always and idrec4 bit 5 - 0 in case of extended frame reception) may be written by the dcan to ? 0 ? . they are not released for other use by the cpu. 2. rtr rec is the received value of the rtr message bit when this buffer is used together with a mask function. by using the mask function a successfully received identifier overwrites the idrec0 and idrec1 registers for standard frame format and the idrec0 to idrec4 registers for extended frame format. for the rtr rec bit exists two modes: rtr bit in the mcon register of the dedicated mask is set to ? 0 ? . in this case rtr rec bit will always be written to ? 0 ? together with the update of the idn bits (n = 18 to 20) in idrec1. the received frame type (data or remote) is defined by the rtr bit in idcon of the buffer. rtr bit in the mcon register of the dedicated mask is set to ? 1 ? (data and remote frames are accepted). in this case the rtr bit in idcon register has no meaning. the received message type passed the mask is shown in rtr rec bit. if a buffer is not dedicated to a mask function (mask 1, mask 2 or global mask) the idrec0 to idrec4 registers are only read for comparing. all receive identifiers should be defined to ? 0 ? before the application sets up its specific values. symbol76543210addressafter resetr/w idrec0 id28 id27 id26 id25 id24 id23 id22 id21 xxx2h undefined r/w idrec1id20id19id180000 rtr rec xxx3h undefined r/w idrec2 id17 id16 id15 id14 id13 id12 id11 id10 xxx4h undefined r/w idrec3 id9 id8 id7 id6 id5 id4 id3 id2 xxx5h undefined r/w idrec4id1id0000000xxx6hundefinedr/w 275 chapter 16 can controller user ? s manual u16504ee1v1ud00 (4) receive message data part these memory locations set the receive message data part of the can protocol. data0 to data7 can be set with a 1-bit or an 8-bit memory manipulation instruction. reset input sets data0 to data7 to an undefined value. figure 16-30: receive data the dcan stores received data bytes in this memory area. only those data bytes which are actually received and match with the identifier are stored in the receive buffer memory area. if the dlc is less than eight, the dcan will not write additional bytes exceeding the dlc value up to eight. the dcan stores a maximum of 8 bytes (according to the can protocol rules) even when the received dlc is greater than eight. symbol76543210addressafter resetr/w data0 xxx8h undefined r/w data1 xxx9h undefined r/w data2 xxxah undefined r/w data3 xxxbh undefined r/w data4 xxxch undefined r/w data5 xxxdh undefined r/w data6 xxxeh undefined r/w data7 xxxfh undefined r/w 276 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.12 mask function receive message buffer 0 and buffer 2 can be switched for masked operation with the mask control register (maskc). in this case the message does not hold message identifier and data of the frame. instead, it holds identifier and rtr mask information for masked compare operations for the next higher message buffer number. in case the global mask is selected, it keeps mask information for all higher message buffer numbers. a mask does not store any information about identifier length. therefore the same mask can be used for both types of frames (standard and extended) during global mask operation. all unused bytes can be used by the cpu for application needs. (1) identifier compare with mask the identifier compare with mask provides the possibility to exclude some bits from the compari- son process. that means each bit is ignored when the corresponding bit in the mask definition is set to one. the setup of the mask control register (maskc) defines which receive buffer is used as a mask and which receive buffer uses which mask for comparison. the mask does not include any information about the identifier type to be masked. this has to be defined within the dedicated receive buffer. therefore a global mask can serve for standard receive buffers at the same time as for extended receive buffer. table 16-22: mask function name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcon n0h rtr n1h unused mrec0 n2h id standard part mrec1 n3h id standard part 0 0 0 0 0 mrec2 n4h id extended part mrec3 n5h id extended part mrec4 n6h id extended part000000 n7h unused n8h unused n9h unused nah unused nbh unused nch unused ndh unused neh unused nfh unused 277 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-31: identifier compare with mask this function implements the so called basic-can behaviour. in this case the type of identifier is fixed to standard or extended by the setup of the ide bit in the receive buffer. the comparison of the rtr bit can also be masked. it is possible to receive data and remote frames on the same masked receive buffer. the following information is stored in the receive buffer: identifier (11 or 29 bit as defined by ide bit) remote bit (rtr rec ) if both frames types (data or remote) can be received by this buffer reserved bits data length code (dlc) data bytes as defined by dlc caution: all writes into the dcan memory are byte accesses. unused bits in the same byte will be written zero. unused bytes will not be written and are free for application use by the cpu. received identifier mask stored in receive buffer 0 or 2 identifier stored in receive buffer compare bit by bit disable compare for masked bits store on equal 278 chapter 16 can controller user ? s manual u16504ee1v1ud00 (2) mask identifier control register (mcon) the memory location labelled mcon sets the mask identifier control bit of the can protocol. mcon can be set with a 1-bit or an 8-bit memory manipulation instruction. reset input sets mcon to an undefined value. figure 16-32: control bits for mask identifier notes: 1. for rtr = 0 the received frame type (data or remote) is defined by the rtr bit in idcon of the dedicated buffer. in this case rtr rec will always be written to ? 0 ? together with the update of the idn bits (n = 18 to 20) in idrec1. 2. in case rtr in mcon is set to ? 1 ? , rtr bit in idcon of the dedicated receive buffer has no meaning. the received message type passed the mask is shown in the rtr rec bit. symbol76543210addressafter resetr/w mcon000000rtr0xxx0hundefinedr/w rtr remote transmission select 0 check rtr bit of received message note 1 1 receive message independent from rtr bit note 2 279 chapter 16 can controller user ? s manual u16504ee1v1ud00 (3) mask identifier definition these memory locations set the mask identifier definition of the dcan. mrec0 to mrec4 can be set with a 1-bit or an 8-bit memory manipulation instruction. reset input sets mrec0 to mrec4 to an undefined value. figure 16-33: mask identifier symbol76543210addressafter resetr/w mrec0 mid28 mid27 mid26 mid25 mid24 mid23 mid22 mid21 xxx2h undefined r/w mrec1mid20mid19mid1800000xxx3hundefinedr/w mrec2 mid17 mid16 mid15 mid14 mid13 mid12 mid11 mid10 xxx4h undefined r/w mrec3mid9mid8mid7mid6mid5mid4mid3mid2 xxx5hundefinedr/w mrec4mid1mid0000000xxx6hundefinedr/w midn mask identifier bit (n = 0...28) 0 check idn bit in idrec0 through idrec4 of received message 1 receive message independent from idn bit 280 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.13 operation of the can controller 16.13.1 can control register (canc) the operational modes are controlled via the can control register canc. canc can be set with a 1-bit or an 8-bit memory manipulation instruction. reset input sets canc to 01h. figure 16-34: can control register (1/2) canc.5 has always to be written as 0. the init is the request bit to control the dcan. init starts and stops the can protocol activities. due to bus activities disabling the dcan is not allowed any time. therefore changing the init bit must not have an immediate effect to the can protocol activities. setting the init bit is a request only. the initstat bit in the canes register reflects if the request has been granted. the registers mcnt, sync0, sync1, and maskc are write protected while init is cleared independently of initstat. any write to these registers when init is set and the initialisation mode is not confirmed by the initstat bit can have unexpected behaviour to the can bus. symbol 7 6 5 <4> 3 <2> 1 <0> address after reset canc rxf txf 0 sofe sofsel sleep stop init ffb0h 01h r r r r/w r/w r/w r/w r/w init request status for operational modes 0 normal operation 1 initialization mode stop stop mode selection 0 normal sleep operation / sleep mode is released when a transition on the can bus is detected 1 stop operation / sleep mode is cancelled only by cpu access. no wake up from can bus sleep sleep/stop request for can protocol 0 normal operation 1 can protocol goes to sleep or stop mode depending on stop bit 281 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-34: can control register (2/2) the clock supply to the dcan is switched off during initialization, dcan sleep, and dcan stop mode. all modes are only accepted while can protocol is in idle state, whereby the crxd pin must be reces- sive (= high level). a sleep or stop request out of idle state is rejected and the wake bit in canes is set. dcan sleep and dcan stop mode can be requested in the same manner. the only difference is that the dcan stop mode prevents the wake up by can bus activity. caution: the dcan sleep or dcan stop mode can not be requested as long as the wake bit in canes is set. the dcan sleep mode is cancelled under following conditions: a) cpu clears the sleep bit. b) any transition while idle state on can bus (stop = 0). c) cpu sets sleep, but can protocol is active due to bus activity. the wake bit in canes is set under condition b) and c). figure 16-35: dcan support the generation of an sofout signal can be used for time measurements and for global time base syn- chronization of different can nodes as a prerequisite for time triggered communication. sofsel start of frame output function select 0 last bit of eof is used to generate the time stamp 1 sof is used to generate the time stamp sofe start of frame enable 0 sofout does not change 1 sofout toggles depending on the selected mode 16 bit timer frc capture register sofc dcan sof data crc eof mux t-ff sofsel sofe receive buffer 4 clear tq last bit of eof sofout 282 chapter 16 can controller user ? s manual u16504ee1v1ud00 sofc is located in the synchronization register sync1. reset and setting of the init bit of canc register clears the sofout to 0. the txf and rxf bits of canc register show the present status of the dcan to the bus. if both bits are cleared, the bus is in idle state. rxf and txf bits are read-only bits. during initialization mode both bits do not reflect the bus status. note: transmission is active until intermission is completed. table 16-23: possible setup of the sofout function sofsel sofc sofe sofout function x x 0 time stamp function disabled 0 x 1 toggles with each eof 101 toggles with each start of frame on the can bus 111 toggles with each start of frame on the can bus. clears sofe bit when dcan starts to store a message in receive buffer 4 table 16-24: transmission / reception flag txf transmission flag 0 no transmission 1 transmission active on can bus note rxf reception flag 0 no data on the can bus 1 reception active on the can bus 283 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-36: time stamp function figure 16-37: sofout toggle function figure 16-38: global time system function valid message other valid or invalid message valid message int object n int object n enable sof edge for capture edge for capture sof sof sof any valid or invalid message enable sof edge for capture sof sof sof any valid or invalid message any valid or invalid message edge for capture edge for capture other valid or invalid message int object n enable sof edge for capture sof sof sof other valid or invalid message valid sync. message buffer 4 edge for capture disable sof 284 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.13.2 dcan error status register this register shows the status of the dcan. canes has to be set with an 8-bit memory manipulation instruction. reset input sets canes to 00h. the reset sets the init-bit in canc register, therefore canes will be read as 08h after reset release. figure 16-39: can error status register (1/3) remark: boff, recs, tecs and initstate are read only bits. caution: don ? t use bit operations on this sfr. the valid, wake and over bits have a special behavior during cpu write operations: writing a ? 0 ? to them do not change them. writing an ? 1 ? clears the associated bit. this avoids any timing conflicts between cpu access and internal activities. an internal set condition of a bit overrides a cpu clear request at the same time. boff is cleared after receiving 128 x 11 bits recessive state (bus idle) or by issuing a hard dcan reset with the tlres bit in the mcntn register note . an interrupt is generated when the boff bit changes its value. recs is updated after each reception. an interrupt is generated when recs changes its value. note: issuing tlres bit may violate the minimum recovery time as defined in iso-11898. symbol7654 3 210address after reset canes boff recs tecs 0 initstate valid wake over ffb4h 00h rrrr r r/wr/wr/w boff bus off flag 0 transmission error counter 285 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-39: can error status register (2/3) tecs is updated after each reception. an interrupt is generated when tecs changes its value. initstate changes with a delay to the init bit in canc register. the delay depends on the current bus activity and the time to set all internal activities to inactive state. this time can be several bit times long. while boff bit is set, a request to go into the initialization mode by setting the init bit is ignored. in this case the initstate bit will not be set until the bus-off state is left. this bit shows valid protocol activities independent from the message definitions and the rxonly bit setting in sync1n register. valid is updated after each reception. the valid bit will be set at the end of the frame when a complete protocol without errors has been detected. cautions: 1. the valid bit is cleared if cpu writes an ? 1 ? to it, or when the init bit in canc register is set. 2. writing a ? 0 ? to the valid bit has no influence. tecs transmission error counter status 0 transmission error counter < 286 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-39: can error status register (3/3) this bit is set and an error interrupt is generated under the following circumstances: a) a can bus activity occurs during dcan sleep mode. b) any attempt to set the sleep bit in the can control register during receive or transmit opera- tion will immediately set the wake bit. the cpu must clear this bit after recognition in order to receive further error interrupts, because the error interrupt line is kept active as long as this bit is set. cautions: 1. the wake bit is cleared to ? 0 ? if cpu writes an ? 1 ? to it, or when the init bit in canc register is set. 2. writing a ? 0 ? to the wake bit has no influence. the overrun condition is set whenever the can can not perform all ram accesses that are necessary for comparing and storing received data or fetching transmitted data. typically, the overrun condition is encountered when the frequency for the macro is too low compared to the programmed baud rate. an error interrupt is generated at the same time. the dcan interface will work properly (i. e. no overrun condition will occur) with the following settings: the dcan clock as defined with the prm bits in the brprs register is set to a minimum of 16 times of the can baudrate and the selected cpu clock (defined in the pcc register) is set to a minimum of 16 times of the baudrate. possible reasons for an overrun condition are: too many messages are defined. dma access to ram area is too slow compared to the can baudrate. the possible reactions of the dcan differ depending on the situation, when the overrun occurs. wake wake up condition 0 normal operation 1 sleep mode has been cancelled or sleep/stop mode request was not granted over overrun condition 0 normal operation 1 overrun occurred during access to ram 287 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.13.3 can transmit error counter this register shows the transmit error counter. tec register can be read with an 8-bit memory manipulation instruction. reset input sets tec to 00h. figure 16-40: transmit error counter the transmit error counter reflects the status of the error counter for transmission errors as it is defined in the can protocol according iso 11898. 16.13.4 can receive error counter this register shows the receive error counter. rec can be read with an 8-bit memory manipulation instruction. reset input sets rec to 00h. figure 16-41: receive error counter the receive error counter reflects the status of the error counter for reception errors as it is defined in the can protocol according iso 11898. table 16-25: possible reactions of the dcan overrun situation when detected dcan behavior cannot get transmit data. next data byte request from protocol. immediate during the frame. the frame itself conforms to the can specification, but its content is faulty. corrupted data or id in the frame. txrqx bit (x = 0, 1) is not cleared. dcan will retransmit the correct frame after synchronization to the bus. cannot store receive data. data storage is ongoing during the six bit of the next frame. data in ram is inconsistent. no receive flags. dn and muc bit may be set in message. cannot get data for id comparison id compare is ongoing during six bits of next frame. message is not received and its data is lost. symbol76543210address after reset tec tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 ffb5h 00h rrrrrrrr symbol76543210address after reset rec rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 ffb6h 00h rrrrrrrr 288 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.13.5 message count register this register sets the number of receive message buffers and allocates the ram area of the receive message buffers, which are handled by the dcan-module. mcnt can be read with an 8-bit memory manipulation instruction. reset input sets mcnt to c0h. figure 16-42: message count register (mcnt) (1/2) this register is readable at any time. write is only permitted when the can is in initialization mode. symbol76543210addressafter reset mcnt cadd1 cadd0 tlres mcnt4 mcnt3 mcnt2 mcnt1 mcnt0 ffb7h c0h r/w r/w r/w r/w r/w r/w r/w r/w mcnt4 mcnt3 mcnt2 mcnt1 mcnt0 receive message count 0 0 0 0 0 setting prohibited 000011 receive buffer 000102 receive buffer 000113 receive buffer 001004 receive buffer 001015 receive buffer 001106 receive buffer 001117 receive buffer 010008 receive buffer 010019 receive buffer 0 1 0 1 0 10 receive buffer 0 1 0 1 1 11 receive buffer 0 1 1 0 0 12 receive buffer 0 1 1 0 1 13 receive buffer 0 1 1 1 0 14 receive buffer 0 1 1 1 1 15 receive buffer 1 0 0 0 0 16 receive buffer 1xxxx setting prohibited, will be automatically changed to 16 289 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-42: message count register (mcnt) (2/2) cautions: 1. issuing tlres bit may violate the minimum recovery time as defined in iso- 11898. 2. if no receive buffer is desired, define one receive buffer and disable this buffer with the redef function. tlres reset function for can protocol machine 0 no reset is issued 1 reset of can protocol machine is issued if dcan is in bus off state, dcan will enter init state (canc.0 = 1 && canes.3 = 1) cadd1 cadd0 dcan address definition 00 setting prohibited 01 10 1 1 f600h to f7dfh (reset value) 290 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.14 baudrate generation (1) bit rate prescaler register this register sets the clock for the dcan (internal dcan clock) and the number of clocks per time quantum (tq). brprs can be set with an 8-bit memory manipulation instruction. reset input sets brprs to 3fh. figure 16-43: bit rate prescaler (1/2) the prmn (n = 0, 1) bits define the clock source for the dcan operation. the prm selector defines the input clock to the dcan macro and influences therefore all dcan activities. writing to the brprs register is only allowed during initialization mode. any write to this register when init bit is set in canc register and the initialization mode is not confirmed by the initstate bit of canes register can cause unexpected behaviour to the can bus. the brprsn bits (n = 0 to 5) define the number of dcan clocks applied for one tq. for brprsn (n = 0 to 5) two modes are available depending on the tlmode bit in the sync1 register. symbol76543210addressafter reset brprs prm1 prm0 brprs5 brprs4 brprs3 brprs2 brprs1 brprs0 ffb8h 3fh r/w r/w r/w r/w r/w r/w r/w r/w prm1 prm0 input clock selector for dcan clock 00 f x is input for dcan 01 f x /2 is input for dcan 10 f x /4 is input for dcan 1 1 cclk is input for dcan 291 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-43: bit rate prescaler (2/2) setting of brprsn (n = 5 to 0) for tlmode = 0: note: the bit rate prescaler value represents the dcan clocks per tq. setting of brprsn (n = 7 to 0) for tlmode = 1: note: when using this setting the user needs to assure that phase segment 2 consists of at least 3 tq. phase segment 2 is given by the difference of dbt - spt each measured in units of tq. brprs7 and brprs6 are located in the maskc register. brprs5 brprs4 brprs3 brprs2 brprs1 brprs0 bit rate prescaler note 000000 2 000001 4 000010 6 000011 8 ...... . ......2 x brprsn[5-0] + 2 ...... . 111010 118 111011 120 111100 122 111101 124 111110 126 111111 128 brprs7 brprs6 brprs5 brprs4 brprs3 brprs2 brprs1 brprs0 bit rate prescaler 00000000 1 note 00000001 2 00000010 3 00000011 4 ...... . ......brprsn[7-0] +1 ...... . 11111010 123 11111011 124 11111100 125 11111101 126 11111110 127 11111111 128 292 chapter 16 can controller user ? s manual u16504ee1v1ud00 (2) synchronization control registers 0 and 1 these registers define the can bit timing. they define the length of one data bit on the can bus, the position of the sample point during the bit timing, and the synchronization jump width. the range of resynchronization can be adapted to different can bus speeds or network characteris- tics. additionally, some modes related to the baud rate can be selected in sync1 register. sync0 and sync1 can be read or written with an 8-bit memory manipulation instruction. reset input sets sync0 to 18h. reset input sets sync1 to 0eh. figure 16-44: synchronization control registers 0 and 1 (1/2) the length of a data bit time is programmable via dbt[4-0]. symbol7 65 4 3210addressafter resetr/w sync0 spt2 spt1 spt0 dbt4 dbt3 dbt2 dbt1 dbt0 ffb9h 18h r/w symbol7 65 4 3210addressafter resetr/w sync1 tlmode sofc samp rxonly sjw1 sjw0 spt4 spt3 ffbah 0eh r/w dbt4 dbt3 dbt2 dbt1 dbt0 data bit time other than under setting prohibited 001118 x tq 010009 x tq 0100110 x tq 0101011 x tq 0101112 x tq 0110013 x tq 0110114 x tq 0111015 x tq 0111116 x tq 1000017 x tq 1000118 x tq 1001019 x tq 1001120 x tq 1010021 x tq 1010122 x tq 1011023 x tq 1011124 x tq 1100025 x tq other than above setting prohibited 293 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-44: synchronization control registers 0 and 1 (2/2) the position of the sample point within the bit timing is defined by spt0n through spt4n. note: the user needs to assure that phase segment 2 (tseg2) consists of at least 3 tq when using this setting. phase segment 2 is given by the difference of dbt - spt each measured in units of tq. sjw0 and sjw1 define the synchronization jump width as specified in iso 11898. spt4 spt3 spt2 spt1 spt0 sample point position other than under setting prohibited 000012 x tq 000103 x tq 000114 x tq 001005 x tq 001016 x tq 001107 x tq 001118 x tq 010009 x tq 0100110 x tq 0101011 x tq 0101112 x tq 0110013 x tq 0110114 x tq 0111015 x tq 0111116 x tq 1000017 x tq other than above setting prohibited tlmode resolution of bit rate prescaler 0 1 unit of brprs[5-0] in brprs register equals 2 dcan clocks, brprs[7-6] in maskc register are disabled (compatible to older macro versions) 1 1 unit of brprs[7-0] in brprs and maskc register equals 2 dcan clocks, brprs[7-6] in maskc register are enabled note sjw1 sjw0 synchronisation jump width 00 1 x tq 01 2 x tq 10 3 x tq 11 4 x tq 294 chapter 16 can controller user ? s manual u16504ee1v1ud00 limits on defining the bit timing the sample point position needs to be programmed between 3tq note and 17tq, which equals a register value of 2 f x baudrate ------------------------ 8 mhz 500 kbaud ----------------------------- 16 = = 295 chapter 16 can controller user ? s manual u16504ee1v1ud00 with tlmode = 1 the following register settings apply: the receive-only mode can be used for baudrate detection. different baudrate configurations can be tested without disturbing other can nodes on the bus. differences to can protocol in the receive-only mode: the mode never sends an acknowledge, error frames or transmit messages. the error counters do not count. the valid bit in canes reports if the dcan interface receives any valid message. samp defines the number of sample points per bit as specified in the iso-11898. sofc works in conjunction with the sofe and sofsel bits in the can control register canc. for detailed information please refer to the bit description of that sfr register and the time function mode. caution: cpu can read sync0/sync1 register at any time. writing to the sync0/sync1 registers is only allowed during initialization mode. any write to this register when init is set and the initialization mode is not confirmed by the initstate bit can have unexpected behavior to the can bus. register values description bit fields brprsn = 00h clock selector = fx prmn = 00b maskcn = 00xx xxxxb brprsn = 0000 0000b sync0n = 6fh can bit in tq = 16 dbtn = 01111b 7 < (fx/baudrate/bit rate prescaler) < 25] sync1n = 1zzz 1101b sample point 75% = 12 tq: sptn = 01011b sjw 25% = 4 tq sjwn = 11b 1 tq equals 1 clock, brprs 6, 7 are enabled tlmode = 1 z depends on the setting of: - number of sampling points - receive only function - use of time stamp or global time system rxonly receive only operation 0 normal operation 1 only receive operation, can does not activate transmit line samp bit sampling 0 sample receive data one time at receive point 1 sample receive data three times and take majority decision at sample point sofc start of frame control 0 sofe bit is independent from can bus activities 1 sofe bit will be cleared when a message for receive message 4 is received and sof mode is selected 296 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.15 function control 16.15.1 transmit control (1) transmit control register this register controls the transmission of the dcan-module. the transmit control register (tcr) provides complete control over the two transmit buffers and their status. it is possible to request and abort transmission of both buffers independently. tcr can be set with a an 8-bit memory manipulation instruction. reset input sets tcr to 00h. figure 16-45: transmit control register (1/2) caution: don't use bit operations on this register. also logical operations (read-modify-write) via software may lead to unexpected transmissions. initiating a transmit request for buffer 1 while txrq0 is already set, is simply achieved by writing 02h or 82h. the status of the bits for buffer 0 is not affected by this write operation. the user defines which buffer has to be send first in the case of both request bits are set. if only one buffer is requested by the txrqn bits (n = 0, 1) bits, txp bit has no influence. txcn (n = 0, 1) shows the status of the first transmission. it is updated when txrqn (n = 0, 1) is cleared. the txan bits (n = 0, 1) allow to free a transmit buffer with a pending transmit request. setting the txan bit (n = 0, 1) by the cpu requests the dcan to empty its buffer by clearing the respective txrqn bit (n = 0, 1). symbol76543210addressafter reset tcr txp 0 txc1 txc0 txa1 txa0 txrq1 txrq0 ffb1h 00h r/w r r r r/w r/w r/w r/w txp transmission priority 0 buffer 0 has priority over buffer 1 1 buffer 1 has priority over buffer 0 txan transmission abort flag 0 write: normal operation read: no abort pending 1 write: aborts current transmission request for this buffer n read: abort is pending txcn transmission complete flag 0 transmit was aborted / no data sent 1 transmit was complete / abort had no effect 297 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-45: transmit control register (2/2) the txan bits (n = 0, 1) have a dual function: 1. the cpu can request an abort by writing a ? 1 ? into the bit. 2. the dcan signals whether such an request is still pending. the bit is cleared at the same time when the txrqn bit (n = 0, 1) is cleared. the abort process does not affect any rules of the can protocol. a frame already started will continue to its end. an abort operation can cause different results dependent on the time it is issued. d) when an abort request is recognized by the dcan before the start of the arbitration for transmit, the txcn bit (n = 0, 1) is reset showing that the buffer was not send to other nodes. e) when the abort request is recognized during the arbitration and the arbitration is lost afterwards, the txcn bit (n = 0, 1) is reset showing that the buffer was not send to other nodes. f) when the abort request is recognized during frame transmission and the transmission ends with an error afterwards, the txcn bit (n = 0, 1) is reset showing that the buffer was not send to other nodes. g) when the abort request is recognized during the frame transmission and transmission ends with- out error. the txcn bit (n = 0, 1) is set showing a successful transfer of the data. i.e the abort request was not issued. in all cases the txrqn bit and the txan bit (n = 0, 1) bit will be cleared at the end of the abort opera- tion, when the transmit buffer is available again. cautions: 1. the bits are cleared when the init bit in canc register is set. 2. writing a 0 to txan (n = 0, 1) bit has no influence 3. do not perform read-modify-write operations on tcr. the txcn bit (n = 0, 1) are updated at the end of every frame transmission or abort. the transmit request bits are checked by the dcan immediately before the frame is started. the order in which the txrqn bit (n = 0, 1) will be set does not matter as long as the first requested frame is not started on the bus. the txrqn bit (n = 0, 1) have dual function: 1. request the transmission of a transmit buffer. 2. inform the cpu whether a buffer is available or if it is still occupied by a former transmit request. setting the transmission request bit requests the dcan to sent the buffer contents onto the bus. the dcan clears the bit after completion of the transmission. completion is either a normal transfer without error or an abort request. txrqn transmission request flag 0 write: no influence read: transmit buffer is free 1 write: request transmission for buffer n read: transmit buffer is occupied by former transmit request 298 chapter 16 can controller user ? s manual u16504ee1v1ud00 an error during the transmission does not influence the transmit request status. the dcan will auto- matically retry the transfer. cautions: 1. the bits are cleared when the init bit in canc is set. a transmission already started will be finished but not retransmitted in case of an error. 2. writing a 0 to txrq0 bit has no influence. 3. do not use bit operations on this register. 4. do not change data in transmit buffer when the corresponding txrq bit is set. 16.15.2 receive control the receive message register mirrors the current status of the first 8 receive buffers. each buffer has one status bit in this register. this bit is always set when a new message is completely stored out of the shadow buffer into the associated buffer. the cpu can easily find the last received message during receive interrupt handling. the bits in this register always correspond to the dn bit in the data buffers. they are cleared when the cpu clears the dn bit in the data buffer. the register itself is read only. (1) receive message register this register shows receptions of messages of the dcan-module. more than one bit set is possi- ble. rmes can be read with a 1-bit or an 8-bit memory manipulation instruction. reset input sets rmes to 00h. figure 16-46: receive message register this register is read only and it is cleared when the init bit in canc register is set. dn0 bit has no meaning when receive buffer 0 is configured for mask operation in the mask control register. dn2 bit has no meaning when receive buffer 2 is configured for mask operation in the mask control register. symbol76543210addressafter reset rmes dn7 dn6 dn5 dn4 dn3 dn2 dn1 dn0 ffb2h 00h rrrrrrrr dn data new bit for message n (n = 0...7) 0 no message received on message n or cpu has cleared dn bit in message n 1 data received in message n that was not acknowledged by the cpu 299 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.15.3 mask control the mask control register defines whether the dcan compares all identifier bits or if some bits are not used for comparison. this functionality is provided by the use of the mask information. the mask infor- mation defines for each bit of the identifier whether it is used for comparison or not. the dcan uses a receive buffer for this information, when it is enabled by the mask control register. in this case this buffer is not used for normal message storage. unused bytes can be used for application needs. (1) mask control register this register controls the mask function applied to any received message. maskc can be written with an 8-bit memory manipulation instruction. reset input sets maskc to 00h. figure 16-47: mask control register (1/2) note: brprs[7 - 6] are only enable if tlmode is set to 1. caution: this register is readable at any time. writing to the maskc register is only allowed during initialization mode. any write to this register when init bit is set and the initialization mode is not confirmed by the initstate bit can have unexpected behavior to the can bus. symbol 7 note 6 note 543210addressafter reset maskc brprs7 brprs6 ssht al 0 global msk1 msk0 ffbbh 00h r/w r/w r/w r/w r r/w r/w r/w msk0 mask 0 enable 0 receive buffer 0 and 1 in normal operation 1 receive buffer 0 is mask for buffer 1 msk1 mask 1 enable 0 receive buffer 2 and 3 in normal operation 1 receive buffer 2 is mask for buffer 3 global enable global mask 0 normal operation 1 highest defined mask is active for all following buffers 300 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-47: mask control register (2/2) the following table shows which compare takes place for the different receive buffers. the id in this table always represents the id stored in the mentioned receive buffer. the table also shows which buffers are used to provide the mask information and therefore do not receive messages. a global mask can be used for standard and extended frames at the same time. the frame type is only controlled by the ide bit of the receiving buffer. ssht al function 0 x single shot mode disabled 10 single shot mode enabled; no re-transmission when an error occurs. transmit message will not be queued for a second transmit request when the arbitration was lost 11 single shot mode enabled; no re-transmission when an error occurs. transmit message will be queued for a second transmit request when the arbitration was lost. brprs7 brprs6 prescaler values 0 0 selects 0 - 64 dcan clocks per time quanta 0 1 selects 65 - 128 dcan clocks per time quanta 1 0 selects 129 - 192 dcan clocks per time quanta 1 1 selects 193 - 256 dcan clocks per time quanta table 16-26: mask operation buffers global msk1 msk0 receive buffer operation 01234-15 x00 compare id compare id compare id compare id compare id normal 001mask0 compare id & mask0 compare id compare id compare id one mask 010 compare id compare id mask1 compare id & mask1 compare id one mask 011mask0 compare id & mask0 mask1 compare id & mask1 compare id tw o m a s k s 101mask0 compare id & mask0 compare id & mask0 compare id & mask0 global mask 110 compare id compare id mask1 compare id & mask1 two normal, rest global mask 111mask0 compare id & mask0 mask1 compare id & mask1 one mask, rest global mask 301 chapter 16 can controller user ? s manual u16504ee1v1ud00 priority of receive buffers during compare it is possible that more than one receive buffer is configured to receive a particular message. for this case an arbitrary rule for the storage of the message into one of several matching receive buffers becomes effective. the priority of a receive buffers depends on its type defined by the setup of the mask register in first place and its number in second place. the rules for priority are: all non-masked receive buffers have a higher priority than the masked receive buffer. lower numbered receive buffers have higher priority. examples : 1. all rx buffers are enabled to receive the same standard identifier 0x7ffh. result: the message with identifier 0x7ffh is stored in rx0. 2. in difference to the previous set up, the mask option is set for rx2. again the message 0x7ffh is stored in buffer in rx0. 3. if additionally rx0 is configured as a mask, the message will be stored in rx4. 302 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.15.4 special functions (1) redefinition control register this register controls the redefinition of an identifier of a received buffer. redef can be written with an 1-bit or an 8-bit memory manipulation instruction. reset input sets redef to 00h. figure 16-48: redefinition control register (1/2) the redefinition register provides a way to change identifiers and other control information for one receive buffer, without disturbing the operation of the other buffers. this bit is cleared when init bit in canc is set. symbol <7> 6 5 4 3 2 1 0 address after reset redef def 0 0 0 sel3 sel2 sel1 sel0 ffb3h 00h r/w r r r r/w r/w r/w r/w def redefine permission bit 0 normal operation 1 receive operation for selected message is disabled. cpu can change definition data for this message. 303 chapter 16 can controller user ? s manual u16504ee1v1ud00 figure 16-48: redefinition control register (2/2) cautions: 1. keep special programming sequence. failing to do so can cause inconsistent data or loss of receive data. 2. do not change def bit and sel bit at the same time. change sel bit only when def bit is cleared. 3. write first sel with def cleared. write than sel with def, or use bit manipulation instruction. only clear def bit by keeping sel or use bit manipulation instruc- tion. setting the redefinition bit removes the selected receive buffer from the list of possible id hits during identifier comparisons. setting the def bit will not have immediate effect, if dcan is preparing to store or is already in progress of storing a received message into the particular buffer. in this case the redefinition request is ignored for the currently processed message. the application should monitor the dn flag before requesting the redefinition state for a particular buffer. a dn flag set indicates a new message that arrived or a new message that is in progress of being stored to that buffer. the application should be prepared to receive a message immediately after redefinition state was set. the user can identify this situation because the data new bit (dn) in the receive buffer will be set. this is of special importance if it is used together with a mask function because in this case the dcan also writes the identifier part of the message to the receive buffer. then the application needs to re-write the configuration of the message buffer. sel3 sel2 sel1 sel0 buffer selection (n =0...15) 0000buffer 0 is selected for redefinition 0001buffer 1 is selected for redefinition 0010buffer 2 is selected for redefinition 0011buffer 3 is selected for redefinition 0100buffer 4 is selected for redefinition 0101buffer 5 is selected for redefinition 0110buffer 6 is selected for redefinition 0111buffer 7 is selected for redefinition 1000buffer 8 is selected for redefinition 1001buffer 9 is selected for redefinition 1010buffer 10 is selected for redefinition 1011buffer 11 is selected for redefinition 1100buffer 12 is selected for redefinition 1101buffer 13 is selected for redefinition 1110buffer 14 is selected for redefinition 1111buffer 15 is selected for redefinition other than above setting prohibited 304 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.16 interrupt information 16.16.1 interrupt vectors the dcan peripheral supports four interrupt sources as shown in the following table. 16.16.2 transmit interrupt the transmit interrupt is generated when all following conditions are fulfilled: the transmit interrupt 0 is generated when txrq0 bit is cleared. the transmit interrupt 1 is generated when txrq1 bit is cleared. clearing of these bits releases the buffer for writing a new message into it. this event can occur due to a successful transmission or due to an abort of a transmission. only the dcan can clear this bit. the cpu can only request to clear the txrqn bit by setting the abortn bit (n = 0, 1). 16.16.3 receive interrupt the receive interrupt is generated when all of the following conditions are fulfilled: can protocol part marks received frame valid. the received frame passes the acceptance filter. in other words, a message buffer with an identifier/mask combination fits to the received frame. the memory access engine successfully stored data in the message buffer. the message buffer is marked for interrupt generation with eni bit set. the memory access engine can delay the interrupt up to the 7th bit of the next frame because of its compare and store operations. table 16-27: interrupt sources function source interrupt flag error error counter overrun error wake up ceif receive received frame is valid crif transmit buffer 0 txrq0 is cleared ctif0 transmit buffer 1 txrq1 is cleared ctif1 305 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.16.4 error interrupt the error interrupt is generated when any of the following conditions are fulfilled: transmission error counter (boff) changes its state. transmission error counter status (tecs) changes its state. reception error counter status (recs) changes its state. overrun during ram access (over) becomes active. the wake-up condition (wake) becomes active. the wake-up condition activates an internal signal to the interrupt controller. in order to receive further error interrupts generated by other conditions, the cpu needs to clear the wake bit in canes register every time a wake-up condition was recognized. no further interrupt can be detected by the cpu as long as the wake bit is set. 306 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.17 influence of the standby function of the can controller 16.17.1 cpu halt mode the cpu halt mode is possible in conjunction with dcan sleep mode. 16.17.2 cpu stop mode the dcan stops any activity when its clock supply stops due to a cpu stop mode issued. this may cause an erroneous behaviour on the can bus. entering the cpu stop mode is not allowed when the dcan is in normal mode, i.e. online to the can bus. the dcan will reach an overrun condition, when it receives clock supply again. cpu stop mode is possible when the dcan was set to initialization state, sleep mode or stop mode beforehand. note that the cpu will not be started again if the dcan stop mode was entered previously. 16.17.3 dcan sleep mode the dcan sleep mode is intended to lower the power consumption during phases where no communi- cation is required. the cpu requests the dcan sleep mode. the dcan will signal with the wake bit, if the request was granted or if it is not possible to enter the sleep mode due to ongoing bus activities. after a successful switch to the dcan sleep mode, the cpu can safely go into halt, watch or stop mode. however, the application needs to be prepared that the dcan cancels the sleep mode any time due to bus activities. if the wake-up interrupt is serviced, the cpu stop mode has not to be issued. otherwise the cpu will not be released from cpu stop mode even when there is ongoing bus activity. the wake-up is independent from the clock. the release time for the cpu stop mode of the device is of no concern because the dcan synchronizes again to the can bus after clock supply has started. 307 chapter 16 can controller user ? s manual u16504ee1v1ud00 the following example sketches the general approach on how to enter the dcan sleep mode. note that the function may not return for infinite time when the can bus is busy. the user may apply time out controls to avoid excessive run-times. code example: dcan_sleep_mode(void){ canes = 0x02; // clear wake bit canc = 0x04 // request dcan sleep mode while (canes & 0x02) // check if dcan sleep mode was accepted { canes = 0x02; // try again to get dcan asleep canc = 0x04; } } the following code example assures a safe transition into cpu stop mode for all timing scenarios of a suddenly occurring bus activity. the code prevents that the cpu gets stuck with its oscillator stopped despite can bus activity. code example: ........ //any application code dcan_sleep_mode; //request and enter dcan sleep mode ........ //any application code di(); //disable interrupts nop; note nop; if (wakeup_interrupt_occurred == false) // the variable wakeup_interrupt occurred // needs to be initialized at system reset // and it needs to be set true when servicing // the wake-up interrupt. { cpu_stop; //enter cpu stop mode } nop: note nop: nop; ei(); // enable interrupts ......... // resume with application code note: the interrupt acknowledge needs some clock cycles (depends on host core). in order to prevent that the variable wakeup_interrupt_occurred is already read before di(); becomes effective some nop-instruction have to be inserted. as well the number of nop-instructions after the cpu stop instruction is dependent on the host core. the given example is tailored for 78k0. 308 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.17.4 dcan stop mode the cpu requests this mode from dcan. the procedure equals the request for dcan sleep mode. the dcan will signal with the wake bit, if the request was granted or if it is not possible to enter the dcan stop mode due to ongoing bus activities. after a successful switch to the dcan stop mode, the cpu can safely go into halt, watch or stop mode without any precautions. the dcan can only be woken up by the cpu. therefore the cpu needs to clear the sleep bit in the canc register. this mode reduces the power consumption of the dcan to a minimum. code example: dcan_stop_mode(void){ canes = 0x02; // clear wake bit canc = 0x06 // request dcan stop mode while (canes & 0x02) // check if dcan stop mode was accepted { canes = 0x02; // try again to get dcan into stop mode canc = 0x06; } } 309 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.18 functional description by flowcharts 16.18.1 initialization figure 16-49: initialization flow chart software init end initialization reset set init=1 in canc set brprs sync0/1 initilialize message and mask data set mcnt maskc clear init=0 in canc write for brprs sync0/1 mcnt maskc is now disabled 310 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.18.2 transmit preparation figure 16-50: transmit preparation transmit txrqn write data select priority txp set txrqn = 1 end transmit = 0 wait or abort or try other buffer = 1 311 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.18.3 abort transmit figure 16-51: transmit abort transmission abort set txan txrqn = 1 txcn = 0 transmit was successful before abort transmit was aborted = 0 end transmission abort = 1 312 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.18.4 handling by the dcan figure 16-52: handling of semaphore bits by dcan-module data storage write dn = 1 muc = 1 write dn = 1 muc = 0 dlc end data storage warns that data will be changed data is changed. muc = 0 signals stable data write identifier bytes only for buffers that are declared for mask operation write data bytes 313 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.18.5 receive event oriented figure 16-53: receive with interrupt, software flow receive interrupt scans rmes or dn bits to find message clear dn bit read or process data dn = 0 and muc = 0 end receive interrupt yes uses clr1 command data was changed by can during the processing clear interrupt no 314 chapter 16 can controller user ? s manual u16504ee1v1ud00 16.18.6 receive task oriented figure 16-54: receive, software polling receive polled clear dn bit read or process data dn = 0 and muc = 0 end receive polled yes uses clr1 command data was changed by can during the processing no 315 user ? s manual u16504ee1v1ud00 chapter 17 lcd controller / driver 17.1 lcd controller/driver functions the functions of the lcd controller/driver incorporated in the pd780828a subseries are listed below. (1) automatic output of segment signals and common signals is possible by automatic reading of the display data memory. (2) display mode 1/4 duty (1/3 bias) (3) any of four frame frequencies can be selected in each display mode. (4) maximum of 28 segment signal outputs (s0 to s27); 4 common signal outputs (com0 to com3). all segment outputs can be switched to input/output ports. p47/s0 to p40/s7 is byte-wise switchable. p87/s8 to p80/s15, p97/s16 to p90/s23 and p37/s24 to p34/s27 are bitwise switchable. the maximum number of displayable pixels is shown in table 17-1. 17.2 lcd controller/driver configuration the lcd controller/driver consists of the following hardware. table 17-1: maximum number of display pixels bias method time division common signals used maximum number of display pixels 1/3 4 com0 to com3 112 (28 segments x 4 commons) table 17-2: lcd controller/driver configuration item configuration display outputs segment signals: 28 segment signal with alternate function: 28 common signals: 4 (com0 to com3) control registers lcd display mode register (lcdm) lcd display control register (lcdc) 316 chapter 17 lcd controller / driver user ? s manual u16504ee1v1ud00 figure 17-1: lcd controller/driver block diagram remark: segment driver figure 17-2: lcd clock select circuit block diagram remarks: 1. lcdcl: lcd clock 2. f lcd : lcd clock frequency internal bus f a64h 7 6 5 4 3 2 1 0 fa67h 7 6 5 4 3 2 1 0 fa68h 7 6 5 4 3 2 1 0 fa7fh 7 6 5 4 3 2 1 0 displa y data memory 3 2 1 0 selector 3 2 1 0 selector 3 2 1 0 selector 3 2 1 0 selector ... ... ... ... ... ... note note note note p77 output buffer s23/p90 s0/p47 ... ... ... ... ... ... ... ... ... ... ... ... ... ... s24/p37 p50 output buffer s27/p34 segment selector common driver com0 com3 com1 com2 v lcd lcdon lcdm6 lcdm5 lcdm4 lcd clock selector f lcd 3 lcd display mode register (lcdm) lips lcd displa y control register (lcdc) ... ... ... ... ... ... ... timing controller p or t function register (pfn) (n = 3, 4, 8, 9) lcd driver voltage controller p90 output buffer p47 output buffer prescaler f lcd /2 3 fx/2 14 f lcd /2 2 f lcd /2 f lcd selector lcdm6 lcdm5 lcdm4 3 lcdcl lcd display mode register internal bus 317 chapter 17 lcd controller / driver user ? s manual u16504ee1v1ud00 17.3 lcd controller/driver control registers the lcd controller/driver is controlled by the following two registers. lcd display mode register (lcdm) lcd display control register (lcdc) (1) lcd display mode register (lcdm) this register enables/disables the lcd and selects the lcd clock. lcdm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears lcdm to 00h. figure 17-3: lcd display mode register (lcdm) format remark: f x = main system clock oscillation frequency (at 8.00 mhz) symbol76543210addressafter resetr/w lcdmlcdonlcdm6lcdm5lcdm40000ff90h00hr/w lcdon lcd enable/disable 0 display off (all segment outputs are non-select signal outputs) 1 display on lcdm6 lcdm5 lcdm4 lcd clock selection (f x = 8.00 mhz) 000 f x /2 17 (61 hz) 001 f x /2 16 (122 hz) 010 f x /2 15 (244 hz) 011 f x /2 14 (488 hz) other than above setting prohibited 318 chapter 17 lcd controller / driver user ? s manual u16504ee1v1ud00 (2) lcd display control register (lcdc) this register sets cutoff of the current flowing to split resistors for lcd drive voltage generation and switchover between segment output and input/output port functions. lcdc is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears lcdc to 00h. figure 17-4: lcd display control register (lcdc) format caution: set bit 7 to 1 and bit 1 to bit 6 to 0. 17.4 lcd controller/driver settings lcd controller/driver settings should be performed as shown below. <1> set the initial value in the display data memory (fa64h to fa7fh). <2> set the pins to be used as segment outputs in port function registers (pf3, pf4, pf8 and pf9). <3> set the lcd power supply in the lcd display control register (lcdc). <4> set the lcd clock in the lcd display mode register (lcdm). next, set data in the display data memory according to the display contents. symbol76543210addressafter resetr/w lcdc1000000lipsff92h00hr/w lips lcd driving power supply selection 0 does not supply power to lcd 1 supplies power to lcd from v dd pin 319 chapter 17 lcd controller / driver user ? s manual u16504ee1v1ud00 17.5 lcd display data memory the lcd display data memory is mapped onto addresses fa64h to fa7fh. the data stored in the lcd display data memory can be displayed on an lcd panel by the lcd controller/driver. figure 17-5 shows the relationship between the lcd display data memory contents and the segment outputs/common outputs. any area not used for display can be used as normal ram note . figure 17-5: relationship between lcd display data memory contents and segment/common outputs caution: the higher 4 bits of the lcd display data memory do not incorporate memory. be sure to set them to 0. remark: the data of s0 is stored at the highest address in the lcd display data memory. note: reset clears the lcd display data memory to 00h. s0/p47 s1/p46 s2/p45 s3/p44 s25/p36 s26/p35 s27/p34 com3 com2 com1 com0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address fa7fh fa7ch fa7dh fa7ch fa66h fa65h fa64h 320 chapter 17 lcd controller / driver user ? s manual u16504ee1v1ud00 17.6 common signals and segment signals an individual pixel on an lcd panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage (the lcd drive voltage v lcd ). the light goes off when the potential difference becomes v lcd or lower. as an lcd panel deteriorates if a dc voltage is applied in the common signals and segment signals, it is driven by ac voltage. (1) common signals for common signals, the selection timing order is as shown in table 17-3, and operations are repeated with these as the cycle. table 17-3: com signals (2) segment signals segment signals correspond to a 28-byte lcd display data memory (fa64h to fa7fh). each dis- play data memory bit 0, bit 1, bit 2, and bit 3 is read in synchronization with the com0, com1, com2 and com3 timings respectively, and if the value of the bit is 1, it is converted to the selec- tion voltage. if the value of the bit is 0, it is converted to the non-selection voltage and send to a segment pin (s0 to s27) (s27 to s0 have an alternate function as input/output port pins). consequently, it is necessary to check what combination of front surface electrodes (correspond- ing to the segment signals) and rear surface electrodes (corresponding to the common signals) of the lcd panel to be used to form the display pattern. then write a bit data corresponding on a one-to-one basis with the pattern to be displayed. bits 4 to 7 are fixed at 0. com signal com0 com1 com2 com3 time division 4-time division 321 chapter 17 lcd controller / driver user ? s manual u16504ee1v1ud00 (3) common signal and segment signal output waveforms the voltages shown in table 17-4 are output in the common signals and segment signals. the v lcd on voltage is only produced when the common signal and segment signal are both at the selection voltage; other combinations produce the off voltage. figure 17-6 shows the common signal waveform, and figure 17-7 shows the common signal and segment signal voltages and phases. figure 17-6: common signal waveform remark: t : one lcdcl cycle tf : frame frequency figure 17-7: common signal and segment signal voltages and phases remark: t : one lcdcl cycle table 17-4: lcd drive voltage segment select level non-select level common v ss1 , v lc0 v lc1 , v lc2 select level v lc0 , v ss1 -v lcd , +v lcd -1/3 v lcd , +1/3 v lcd non-select level v lc2 , v lc1 -1/3 v lcd , +1/3 v lcd -1/3 v lcd , +1/3 v lcd t f = 4 x t comn (divided by 4) v lc0 v ss v lcd v lc1 v lc2 selected not selected common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt v lc2 v lc2 v lc1 v lc1 322 chapter 17 lcd controller / driver user ? s manual u16504ee1v1ud00 17.7 supplying lcd drive voltage v lc0 , v lc1 , and v lc2 the pd780828a subseries have a split resistor to create an lcd drive voltage, and the drive voltage is fixed to 1/3 bias. to supply various lcd drive voltages, internal v dd or external v lcd supply voltage can be selected. figure 17-8 shows an example of supplying an lcd drive voltage from an internal source according to table 17-5. figure 17-8: example of connection of lcd drive power supply (1/2) (a) to supply lcd drive voltage from v dd table 17-5: lcd drive voltage supply bias method 1/3 bias method lcd drive voltage v lc0 v lc0 v lc1 2/3 v lc0 v lc2 1/3 v lc0 v dd v ss v lcd = v dd p-ch lips (= 1) r r r v ss v lc2 v lc1 v lc0 v lcd leave v lcd pin open 323 chapter 17 lcd controller / driver user ? s manual u16504ee1v1ud00 figure 17-8: example of connection of lcd drive power supply (2/2) (b) to supply lcd drive voltage from external source v dd v lcd v dd r 1 r 2 v ss v ss v lcd =x v dd p-ch lips (= 0) r r r v ss v lc2 v lc1 v lc0 v lcd 3r r 2 3r r 2 + 3r r 1 + r 1 r 2 324 chapter 17 lcd controller / driver user ? s manual u16504ee1v1ud00 17.8 display mode 17.8.1 4-time-division display example figure 17-10, ? 4-time-division lcd panel connection example, ? on page 325 shows the relationship between a 4-time-division type 10-digit lcd panel and the display pattern shown in figure 17-9, ? 4- time-division lcd display pattern and electrode connections, ? on page 324 and the pd780828a subseries segment signals (s0 to s19) in conjunction with common signals (com0 to com3). the dis- play example is ? 1234567890 ? . the display data memory contents (addresses fa7fh to fa6ch) corre- spond to this. an explanation is given here taking the example of the 5th digit ? 6 ? ( ). in accordance with the display pattern in figure 17-9, ? 4-time-division lcd display pattern and electrode connections, ? on page 324, selection and non-selection voltages must be send to pins s8 and s9 as shown in table 17-6 at the com0 to com3 common signal timings. remark: s: selection, ns: non-selection from this, it can be seen that 0101 (com0 is lsb) must be prepared in the display data memory (address fa77h) corresponding to s8. examples of the lcd drive waveforms between s8 and the com0 and com1 signals are shown in fig- ure 17-11, ? 4-time-division lcd drive waveform examples (1/3 bias method), ? on page 326 (for the sake of simplicity, waveforms for com2 and com3 have been omitted). when s8 carries the selection voltage at the com0 selection timing, it can be seen that the +v lcd / ? v lcd ac square wave, which is the lcd illumination (on) level, is generated. figure 17-9: 4-time-division lcd display pattern and electrode connections remark: n = 0 to 9 table 17-6: selection and non-selection voltages (com0 to com3) segment s8 s9 common com0 s s com1 ns s com2 s s com3 ns s com0 s 2n com1 s 2n + 1 com2 com3 325 chapter 17 lcd controller / driver user ? s manual u16504ee1v1ud00 figure 17-10: 4-time-division lcd panel connection example timing strobes com3 com2 com1 com0 bit0 bit1 bit2 bit3 s0 s1 s2 s3 1 1 0 fa7fh 1 1 1 e 1 1 0 d 1 0 0 c s4 s5 s6 s7 1 1 0 b 1 1 1 a 1 1 0 9 1 0 0 8 s8 s9 s10 s11 1 1 0 7 1 1 1 6 1 1 0 5 1 0 1 4 s12 s13 s14 s15 0 1 0 3 1 0 0 2 1 1 0 1 0 0 1 0 s16 s17 s18 s19 1 0 0 fa6fh 0 1 1 e 0 1 0 d 0 0 0 fa6ch data memor y address lcd panel 1 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0 326 chapter 17 lcd controller / driver user ? s manual u16504ee1v1ud00 figure 17-11: 4-time-division lcd drive waveform examples (1/3 bias method) t f v lc0 v lc2 com0 +v lcd 0 com0 to s8 ? v lcd v lc1 +1/3v lcd ? 1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 com3 v lc1 v ss +v lcd 0 com1 to s8 ? v lcd +1/3v lcd ? 1/3v lcd v lc0 v lc2 s8 v lc1 v ss 327 chapter 17 lcd controller / driver user ? s manual u16504ee1v1ud00 17.9 cautions on emulation to perform debugging with an in-circuit emulator, the lcd timer control register (lcdtm) must be set. lcdtm is a register used to figure the i/o board (ie-78k0-ns-p04) appropriately. 17.9.1 lcd timer control register (lcdtm) lcdtm is a write-only register that controls supply of the lcd-clock. unless lcdtm is set, the lcd controller/ driver does not operate. therefore, set bit 1 (tmc21) of lcdtm to 1 when using the lcd controller/driver. figure 17-12: lcd timer control register (lcdtm) format cautions: 1. lcdtm is a special register that must be set when debugging is performed with an in-circuit emulator. even if this register is used, the operation of the pd780828a subseries is not affected. however, delete the instruction that manipulates this register from the program at the final stage of debugging. 2. bits 7 to 2, and bit 0 must be set to 0. symbol76543210addressafter resetr/w lcdtm100000tmc210ff93h00hw tmc21 lcd clock supply control 0 lcd controller/driver stop mode (supply of lcd clock is stopped) 1 lcd controller/driver operating mode (supply of lcd clock is enabled) 328 user ? s manual u16504ee1v1ud00 [memo] 329 user ? s manual u16504ee1v1ud00 chapter 18 sound generator 18.1 sound generator function the sound generator has the function to operate an external speaker. the following two signals are supplied by the sound generator. (1) basic cycle output signal (with/without amplitude) a buzzer signal with a variable frequency in a range of 0.5 to 3.8 khz (at f x = 8.38 mhz) can be created. the amplitude of the basic cycle output signal can be varied by anding the basic cycle output signal with the 7-bit-resolution pwm signal, to achieve control of the volume. (2) amplitude output signal a pwm signal with a 7-bit resolution for variable amplitude can be generated independently. figure 19-1 shows the sound generator block diagram and figure 19-2 shows the concept of each sig- nal. figure 18-1: sound generator block diagram inter nal bus inter nal bus sound generator control register (sgcr) tce 2 4 7 q f x f sg1 f sg2 1/2 1/2 selector prescaler selector selector 5-bit counter comparator comparator sgo/ sgof/ p60 pcl/ sgoa/ p61 clear pwm amplitude s r sgob sgcl0 sgam3 p61 output latch clock output control circuit (pcl) pm61 sound generator buzzer control register (sgbr) sgcl0 sgcl2 sgcl1 sgob sgbr3 sgbr2 sgbr1 sgbr0 sgam4 sgam5 sgam2 sgam1 sgam6 sgam0 sound generator amplitude register (sgam) port mode register 6 (pm6) 330 chapter 18 sound generator user ? s manual u16504ee1v1ud00 figure 18-2: concept of each signal 18.2 sound generator configuration the sound generator consists of the following hardware. 18.3 sound generator control registers the following three types of registers are used to control the sound generator. sound generator control register (sgcr) sound generator buzzer control register (sgbr) sound generator amplitude control register (sgam) table 18-1: sound generator configuration item configuration counter 8 bits x 1, 5 bits x 1 sg output sgo/sgof (with/without append bit of basic cycle output) sgoa (amplitude output) control register sound generator control register (sgcr) sound generator buzzer control register (sgbr) sound generator amplitude register (sgam) basic cycle output sgof (without amplitude) amplitude output sgoa basic cycle output sgo (with amplitude) 331 chapter 18 sound generator user ? s manual u16504ee1v1ud00 (1) sound generator control register (sgcr) sgcr is a register which sets up the following four types. controls sound generator output selects output of sound generator selects sound generator input frequency f sg1 selects 5-bit counter input frequency f sg2 sgcr is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sgcr to 00h. figure 18-3 shows the sgcr format. figure 18-3: sound generator control register (sgcr) format (1/2) caution: before setting the tce bit, set all the other bits. remark: sgof : basic cycle signal (without amplitude) sgo : basic cycle signal (with amplitude) sgoa : amplitude signal symbol76543210addressafter resetr/w sgcr tce 0 0 0 sgob sgcl2 sgcl1 sgcl0 ffc0h 00h r/w tce sound generator output selection 0 timer operation stopped sgof/sgo and sgoa for low-level output 1 sound generator operation sgof/sgo and sgoa for output sgob sound generator output selection 0 selects sgof and sgoa outputs 1 selects sgo and pcl outputs sgcl2 sgcl1 5-bit counter input frequency f sg2 selection 00 f sg2 = f sg1 /2 5 01 f sg2 = f sg1 /2 6 10 f sg2 = f sg1 /2 7 11 f sg2 = f sg1 /2 8 332 chapter 18 sound generator user ? s manual u16504ee1v1ud00 figure 18-3: sound generator control register (sgcr) format (2/2) cautions: 1. when rewriting sgcr to other data, stop the timer operation (tce = 0) beforehand. 2. bits 4 to 6 must be set to 0. the sound generator output frequency f sg can be calculated by the following expression. f sg = 2 (sgcl0 ? sgcl1 ? 2 ? 7) ? 0 ? 2 ? 7) table 18-2: maximum and minimum values of the buzzer output frequency sgcl2 sgcl1 sgcl0 maximum and minimum values of buzzer output f sg2 f x = 8 mhz f x = 8.38 mhz max. (khz) min. (khz) max. (khz) min. (khz) 000 f sg1 /2 6 3.677 1.953 3.851 2.046 001 f sg1 /2 5 7.354 3.906 7.702 4.092 010 f sg1 /2 7 1.838 0.976 1.926 1.024 011 f sg1 /2 6 3.677 1.953 0.481 2.046 100 f sg1 /2 8 0.919 0.488 0.963 0.512 101 f sg1 /2 7 1.838 0.976 1.926 1.024 110 f sg1 /2 9 0.460 0.244 0.481 0.256 111 f sg1 /2 8 0.919 0.488 0.963 0.512 333 chapter 18 sound generator user ? s manual u16504ee1v1ud00 (2) sound generator buzzer control register (sgbr) sgbr is a register that sets the basic frequency of the sound generator output signal. sgbr is set with an 8-bit memory manipulation instruction. reset input clears sgbr to 00h. figure 18-4 shows the sgbr format. figure 18-4: sound generator buzzer control register (sgbr) format note: output frequency where sgcl0, sgcl1, and sgcl2 are 0, 0, and 0. cautions: 1. when rewriting sgbr to other data, stop the timer operation (tce = 0) beforehand. 2. bits 4 to 7 must be set to 0. (3) sound generator amplitude register (sgam) sgam is a register that sets the amplitude of the sound generator output signal. sgam is set with an 8-bit memory manipulation instruction. reset input clears sgam to 00h. figure 18-5 shows the sgam format. symbol76543210addressafter resetr/w sgbr0000sgbr3sgbr2sgbr1sgbr0ffc2h00hr/w sgbr3 sgbr2 sgbr1 sgbr0 buzzer output frequency (khz) note f x = 8 mhz) f x = 8.38 mhz) 0 0 0 0 3.677 3.851 0 0 0 1 3.472 3.637 0 0 1 0 3.290 3.446 0 0 1 1 3.125 3.273 0 1 0 0 2.976 3.117 0 1 0 1 2.841 2.976 0 1 1 0 2.717 2.847 0 1 1 1 2.604 2.728 1 0 0 0 2.500 2.619 1 0 0 1 2.404 2.518 1 0 1 0 2.315 2.425 1 0 1 1 2.232 2.339 1 1 0 0 2.155 2.258 1 1 0 1 2.083 2.182 1 1 1 0 2.016 2.112 1 1 1 1 1.953 2.046 334 chapter 18 sound generator user ? s manual u16504ee1v1ud00 figure 18-5: sound generator amplitude register (sgam) format cautions: 1. when rewriting the contents of sgam, the timer operation does not need to be stopped. however, note that a high level may be output for one period due to rewrite timing. 2. bit 7 must be set to 0. symbol76543210addressafter resetr/w sgam 0 sgam6 sgam5 sgam4 sgam3 sgam2 sgam1 sgam0 ffc1h 00h r/w sgam6 sgam5 sgam4 sgam3 sgam2 sgam1 sgam0 amplitude 0000000 0/128 0000001 2/128 0000010 3/128 0000011 4/128 0000100 5/128 0000101 6/128 0000110 7/128 0000111 8/128 0001000 9/128 0001001 10/128 0001010 11/128 0001011 12/128 0001100 13/128 0001101 14/128 0001110 15/128 0001111 16/128 0010000 17/128 0010001 18/128 0010010 19/128 0010011 20/128 0010100 21/128 0010101 22/128 0010110 23/128 0010111 24/128 0011000 25/128 0011001 26/128 0011010 27/128 0011011 28/128 0011100 29/128 0011101 30/128 0011110 31/128 || 1111111128/128 335 chapter 18 sound generator user ? s manual u16504ee1v1ud00 18.4 sound generator operations 18.4.1 to output basic cycle signal sgof (without amplitude) select sgof output by setting bit 3 (sgob) of the sound generator control register (sgcr) to ? 0 ? . the basic cycle signal with a frequency specified by the sgcl0 to sgcl2 and sgbr0 to sgbr3 is output. at the same time, the amplitude signal with an amplitude specified by the sgam0 to sgam6 is output from the sgoa pin. figure 18-6: sound generator output operation timing timer comparator 1 coincidence sgof sgoa nnnnnn 336 chapter 18 sound generator user ? s manual u16504ee1v1ud00 18.4.2 to output basic cycle signal sgo (with amplitude) select sgo output by setting bit 3 (sgob) of the sound generator control register (sgcr) to ? 1 ? . the basic cycle signal with a frequency specified by the sgcl0 to sgcl2 and sgbr0 to sgbr3 is output. when sgo output is selected, the sgoa pin can be used as a pcl output (clock output) or i/o port pin. figure 18-7: sound generator output operation timing timer comparator 1 sgof sgoa sgo nnnnnn coincidence 337 user ? s manual u16504ee1v1ud00 chapter 19 meter controller / driver 19.1 meter controller/driver functions the meter controller/driver is a function to drive a stepping motor for external meter control or cross coil. can set pulse width with a precision of 8 bits can set pulse width with a precision of 8 + 1 bits with 1-bit addition function can drive up to four 360 type meters figure 19-1 shows the block diagram of the meter controller/driver. figure 19-2 shows 1-bit addition circuit block diagram. figure 19-1: meter controller/driver block diagram remark: n = 1 to 4 the meter controller/driver is a peripheral to control/drive up to four external meters (stepper motor/ cross coil motors). internal bus internal bus pcs pce modn enn timer mode control register (mcntc) port mode control register (pmc) selector 8-bit timer register fx/2 modn enn 1-bit addition circuit compare register (mcmpn0) s q r output control circuit smn1(sin+) smn2(sin-) 1-bit addition circuit compare register (mcmpn1) s q r output control circuit smn3(cos+) smn4(cos-) modn enn tenn adbn1 adbn0 dirn1 dirn0 compare control register n (mcmpcn) 2 2 ovf fcc selector fx/8 fx/16 fx/64 fx/128 fx/256 fx/512 tm52out fx smcl2 smcl1 smcl0 meter c/d clock selection (smswi) 338 chapter 19 meter controller / driver user ? s manual u16504ee1v1ud00 figure 19-2: 1-bit addition circuit block diagram remark: n = 1 to 4, m = 0, 1 19.2 meter controller/driver configuration the meter controller/driver consists of the following hardware. remark: n = 1 to 4 table 19-1: meter controller/driver configuration item configuration timer free-running up counter (smcnt): 1 channel register compare register (mcmpn1, mcmpn0): 8 channels control registers timer mode control register (mcntc) compare control register n (mcmpcn) port mode control register (pmc) pulse control circuit 1-bit addition circuit/output control circuit internal bus f cc ovf compare register (mcmpnm) q s r q s selector adbn1 adbn0 compare control register (mcmpcn) 2 339 chapter 19 meter controller / driver user ? s manual u16504ee1v1ud00 (1) free running up counter (smcnt) mcnt is an 8-bit free running counter. it is also a register that executes an increment at the rising edge of the input clock. a pwm pulse with a resolution of 8 bits can be created. the duty factor can be set in a range of 0 to 100%. the count value is cleared in the following cases. when reset signal input when counter stops (pce = 0) (2) compare register n0 (mcmpn0) mcmpn0 is an 8-bit register that can rewrite a complete value according to the specification by bit 4 (tenn) of the compare control register n (mcmpcn). the values of these registers are cleared to 00h at reset. the hardware is cleared to 0 by reset . mcmpn0 is a register that supports read/write only for 8-bit access instructions. mcmpn0 continuously compares its value with the smcnt value. when the two values match, a match signal on the sin side of the meter n is generated. (3) compare register n1 (mcmpn1) mcmpn1 is an 8-bit register that can rewrite compare values through specification of bit 4 (tenn) of compare control register n (mcmpcn). reset input sets this register to 00h and clears hardware to 0. mcmpn1 is a register that sup- ports read/write only for 8-bit access instructions. mcmpn1 compares its value with the smcnt value. when the two values match, a match signal on cos side of the meter n is generated. (4) 1-bit addition circuit the 1-bit addition circuit repeats 1-bit addition/non-addition to the pwm output alternately upon mcnt overflow, and enables the state of the pwm output between the current compare value and the next compare value. this circuit is controlled by bits 2 and 3 (adbn0, adbn1) of the mcmpcn register. 340 chapter 19 meter controller / driver user ? s manual u16504ee1v1ud00 (5) output control circuit this circuit consists of a pch and nch drivers and can drive a meter in h bridge configuration by connecting a coil. when a meter is driven in half bridge configuration, the unused pins can be used as normal output port pins. the relation of the duty factor of the pwm signal output from the smnm pin is indicated by the following expression (n = 1 to 4, m = 0, 1). cautions: 1. mcmpn0 and mcmpn1 cannot be read or written by a 16-bit access instruction. 2. mcmpn0 and mcmpn1 are in master-slave configuration, and smcnt is com- pared with a slave register. the pwm pulse is not generated until the first over- flow occurs after the counting operation has been started because the compare data is not transferred to the slave. (6) meter controller/driver clock switch the input clock of the meter controller/driver can be selected with the meter controller/driver clock switch. by default the register is set to 00h of reset . smswi is a register that supports read/write only as 8-bit instruction. pwm (duty) = set value of mcmpnm 341 chapter 19 meter controller / driver user ? s manual u16504ee1v1ud00 19.3 meter controller/driver control registers the meter controller/driver is controlled by the following three registers. timer mode control register (mcntc) compare control register n (mcmpcn) port mode control register (pmc) remark: n = 1 to 4 (1) timer mode control register (mcntc) mcntc is an 8-bit register that controls the operation of the free-running up counter (smcnt). mcntc is set with an 8-bit memory manipulation instruction. reset input clears mcntc to 00h. figure 19-3 shows the mcntc format. figure 19-3: timer mode control register (mcntc) format cautions: 1. when rewriting mcntc to other data, stop the timer operation (pce=0) beforehand. 2. bits 0 to 3, 6, and 7 must be set to 0. symbol76543210addressafter resetr/w mcntc00pcspce0000ffbfh00hr/w pcs timer counter clock selection 0 selection via smswi register 1 f x /2 pce timer operation control 0 operation stopped (timer value is cleared) 1 operation enabled 342 chapter 19 meter controller / driver user ? s manual u16504ee1v1ud00 (2) compare control register (mcmpcn) mcmpcn is an 8-bit register that controls the operation of the compare register and output direction of the pwm pin. mcmpcn is set with an 8-bit memory manipulation instruction. reset input clears mcmpcn to 00h. figure 19-4 shows the mcmpcn format. figure 19-4: compare control register n (mcmpcn) format remark: n = 1 to 4 note: tenn functions as a control bit and status flag. as soon as the timer overflows and pwm data is output, tenn is cleared to ? 0 ? by hardware. the relation among the dirn1 and dirn0 bits of the mcmpcn register and output pin is shown below. caution: bits 5 to 7 must be set to 0. symbol76543210addressafter resetr/w mcmpcn 0 0 0 tenn adbn1 adbn0 dirn1 dirn0 ffcch to ffcfh 00h r/w tenn note enables transfer by register from master to slave 0 disables data transfer from master to slave. new data can be written. 1 transfer data from master to slave when smcnt overflows. new data cannot be written. adbn1 control of 1-bit addition circuit (cos side of meter n) 0 no 1-bit addition to pwm output 1 1-bit addition to pwm output adbn0 control of 1-bit addition circuit (sin side of meter n) 0 no 1-bit addition to pwm output 1 1-bit addition to pwm output dirn1 dirn2 direction control bit smn1 smn2 smn3 smn4 0 0 pwm 0 pwm 0 01pwm0 0pwm 1 0 0pwm0pwm 11 0pwmpwm0 343 chapter 19 meter controller / driver user ? s manual u16504ee1v1ud00 (3) port mode control register (pmc) pmc is an 8-bit register that specifies pwm/port output. pmc is set with an 8-bit memory manipulation instruction. reset input clears pmc to 00h. figure 19-5 shows the pmc format. figure 19-5: port mode control register (pmc) format (1/2) symbol76543210addressafter resetr/w pmc mod4 mod3 mod2 mod1 en4 en3 en2 en1 ffcbh 00h r/w mod4 meter 4 full/half bridge selection 0 meter 4 output is full bridge 1 meter 4 output is half bridge mod3 meter 3 full/half bridge selection 0 meter 3 output is full bridge 1 meter 3 output is half bridge mod2 meter 2 full/half bridge selection 0 meter 2 output is full bridge 1 meter 2 output is half bridge mod1 meter 1 full/half bridge selection 0 meter 1 output is full bridge 1 meter 1 output is half bridge en4 meter 4 port/pwm mode selection 0 meter 4 output is in port mode 1 meter 4 output is in pwm mode en3 meter 3 port/pwm mode selection 0 meter 3 output is in port mode 1 meter 3 output is in pwm mode 344 chapter 19 meter controller / driver user ? s manual u16504ee1v1ud00 figure 19-5: port mode control register (pmc) format (2/2) the relation among the enn and modn bits of the pmc register, dirn1 and dirn0 bits of the mcmpcn register, and output pins is shown below. dirn1 and dirn0 address the quadrant of sin and cos. dirn1 and dirn0 = 00 through 11 correspond to quadrants 1 through 4, respectively. the pwm signal is routed to the specific pin with respect to the sin/cos of each quadrant. when enn = 0, all the output pins are used as port pins regardless of modn, dirn1 and dirn0. when enn = 1 and modn = 0, the full bridge mode is set, and 0 a pin that does not output a pwm signal is ? 0 ? . when enn = 1 and modn = 1, the half bridge mode is set, and the pin that does not output a pwm signal is used as a port pin. caution: the output polarity of the pwm output changes when smcnt overflows. (4) meter controller/driver clock register (smswi) smswi is an 8-bit register that specifies the input clock of the meter controller/driver. smswi is set with an 8-bit memory manipulation instruction. reset input sets smswi to 00h. figure 19-6 shows the smswi format. en2 meter 2 port/pwm mode selection 0 meter 2 output is in port mode 1 meter 2 output is in pwm mode en1 meter 1 port/pwm mode selection 0 meter 1 output is in port mode 1 meter 1 output is in pwm mode enn modn dirn1 dirn0 smn1 (sin +) smn2 (sin -) smn3 (cos +) smn4 (cos -) mode 0 x x x port port port port port mode 1 0 0 0 pwm gnd pwm gnd pwm mode full bridge 1001pwmgndgndpwm 1 0 1 0 gnd pwm gnd pwm 1011gndpwmpwmgnd 1 1 0 0 pwm port pwm port pwm mode half bridge 1 1 0 1 pwm port port pwm 1 1 1 0 port pwm port pwm 1 1 1 1 port pwm pwm port 345 chapter 19 meter controller / driver user ? s manual u16504ee1v1ud00 figure 19-6: meter controller/driver clock register (smswi) format symbol76543210addressafter resetr/w smswi00000smcl2smcl1smcl0ffbdh00hr/w smcl2 smcl1 smcl0 meter controller/driver clock switch 000 f x 001 f x /8 010 f x /16 011 f x /64 100 f x /128 101 f x /256 110 f x /512 1 1 1 tm52 output 346 chapter 19 meter controller / driver user ? s manual u16504ee1v1ud00 19.4 meter controller/driver operations 19.4.1 basic operation of free-running up counter (smcnt) the free-running up counter is clocked by the count clock selected by the pcs bit of the time mode control register. the value of smcnt is cleared by reset input. the counting operation is enabled or disabled by the pce bit of the timer mode control register (mcntc). figure 19-7 shows the timing from count start to restart. figure 19-7: restart timing after count stop (count start count stop count start) remark: n = 00h to ffh clk mcnt pce 0h 1h 2h 1h 2h 3h 4h n n + 1 00h count start count stop count start 347 chapter 19 meter controller / driver user ? s manual u16504ee1v1ud00 19.4.2 update of pwm data confirm that bit 4 (tenn) of mcmpcn is 0, wait for more than one pwm clock cycle (as selected in smswi register), and then write 8-bit pwm data to mcmpn1, mcmpn, and adbn1 and adbn0 of mcmpcn. at the same time, set tenn to 1. the data will be automatically transferred to the slave latch when the timer overflows, and the pwm data becomes valid. at the same time, tenn is automatically cleared to 0. figure 19-8: update of pwm data tenn = 0 ? no yes wait > 1 pwm clock cycle while mcmpcn data tenn = 1 348 chapter 19 meter controller / driver user ? s manual u16504ee1v1ud00 19.4.3 operation of 1-bit addition circuit figure 19-9: timing in 1-bit addition circuit operation the 1-bit addition mode repeats 1-bit addition/non-addition to the pwm output every second smcnt overflow. therefore, the falling edge of the pwm output signal will occur at compare value n and com- pare value n+1 alternately. a 1-bit addition to the pwm output is applied by setting adbn of the mcm- pcn register to 1. in 1-bit non-addition mode the falling edge of the pwm output signal will always occur at compare value n+1 of smcnt. a 1-bit non-addition (normal output) is applied by setting adbn to 0. remark: n = 1 to 4 smcnt value ovf (overflow) match signal of expected value n pwm output of expected value n (1-bit non-addition) pwm output of expected value n (1-bit addition) pwm output of expected value n+1 (1-bit non-addition) ffh 00h 01h n 349 chapter 19 meter controller / driver user ? s manual u16504ee1v1ud00 19.4.4 pwm output operation (output with 1 clock shifted) figure 19-10: timing of output with 1 clock shifted if the wave of sin and cos of meters 1 to 4 rises and falls internally as indicated by the broken line, the sm11 to sm44 pins always shift the count clock by 1 clock. the output signals are generated in order to prevent v dd /gnd from fluctuating. count clock meter 1 sin (sm11, sm12) meter 1 cos (sm13, sm14) meter 2 sin (sm21, sm22) meter 2 cos (sm23, sm24) meter 3 sin (sm31, sm32) meter 3 cos (sm33, sm34) meter 4 sin (sm41, sm42) meter 4 cos (sm43, sm44) 350 user ? s manual u16504ee1v1ud00 [memo] 351 user ? s manual u16504ee1v1ud00 chapter 20 interrupt functions 20.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally even in a disabled state. it does not undergo inter- rupt priority control and is given top priority over all other interrupt requests. it generates a standby release signal. the non-maskable interrupt has one source of interrupt request from the watchdog timer. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register (pr0l, pr0h, and pr1l). multiple high priority interrupts can be applied to low priority interrupts. if two or more interrupts with the same priority are simultaneously generated, each interrupts has a predetermined priority (see table 20-1, ? interrupt source list, ? on page 352). a standby release signal is generated. the maskable interrupt has seven sources of external interrupt requests and fifteen sources of internal interrupt requests. (3) software interrupt this is a vectored interrupt to be generated by executing the brk instruction. it is acknowledged even in a disabled state. the software interrupt does not undergo interrupt priority control. 352 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 20.2 interrupt sources and configuration there are total of 24 interrupt sources: non-maskable, maskable, and software interrupts. notes: 1. default priorities are intended for two or more simultaneously generated maskable interrupt requests. 0 is the highest priority and 22 is the lowest priority. 2. basic configuration types (a) to (d) correspond to (a) to (d) of figure 20-1on page 353. table 20-1: interrupt source list mask- ability interrupt priority note 1 interrupt source internal/ external vector address basic structure ty p e note 2 name trigger non- maskable _intwdt overflow of watchdog timer (when the watchdog timer nmi is selected) internal 0004h (a) maskable 0intwdt overflow of watchdog timer (when the interval timer mode is selected) (b) 1 intad end of a/d converter conversion 0006h 2 intovf overflow of 16-bit timer 2 0008h 3 inttm20 generation of 16-bit timer capture register (cr20) match signal 000ah 4 inttm21 generation of 16-bit timer capture register (cr21) match signal 000ch 5 inttm22 generation of 16-bit timer capture register (cr22) match signal 000eh 6intp0 pin input edge detection external 0010h (c) 7 intp1 0012h 8 intp2 0014h 9 intce can error internal 0016h (b) 10 intcr can receive 0018h 11 intct0 can transmit buffer 0 001ah 12 intct1 can transmit buffer 1 001ch 13 intcsi30 end of serial interface channel 30 (sio30)transfer 001eh 14 intser0 channel 1 uart reception error generation 0020h 15 intsr0 end of channel 1 uart reception 0022h 16 intst0 end of channel 1 uart transfer 0024h 17 inttm50 generation of 8-bit timer/event counter 50 match signal 0026h 18 inttm51 generation of 8-bit timer/event counter 51 match signal 0028h 19 inttm52 generation of 8-bit timer 52 match signal 002ah 002ah 20 intwti reference time interval signal from watch timer 002eh 21 intwt reference time interval signal from watch timer 0030h 22 intcsi31 end of serial interface channel 31 (sio31) transfer 0032h software _ brk brk instruction execution internal 003eh (d) 353 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 figure 20-1: basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt remark: if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specify flag internal bus priority control circuit vector table address generator standby release signal interrupt request internal bus ie pr isp mk if interrupt request priority control circuit vector table address generator standby release signal 354 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 figure 20-1: basic configuration of interrupt function (2/2) (c) external maskable interrupt (except intp0) (d) software interrupt remark: if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specify flag external interrupt mode register (egn, egp) edge detector interrupt request ie pr isp mk if priority control circuit vector table address generator standby release signal internal bus internal bus priority control circuit vector table address generator interrupt request 355 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 20.3 interrupt function control registers the following six types of registers are used to control the interrupt functions. interrupt request flag register (if0l, if0h, if1l) interrupt mask flag register (mk0l, mk0h, mk1l) priority specify flag register (pr0l, pr0h, pr1l) external interrupt mode register (egp, egn) program status word (psw) table 20-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specify flags corre- sponding to interrupt request sources. table 20-2: various flags corresponding to interrupt request sources interrupt request signal name interrupt request flag interrupt mask flag priority specify flag intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intovf ovfif ovfmk ovfpr inttm20 tmif20 tmmk20 tmpr20 inttm21 tmif21 tmmk21 tmpr21 inttm22 tmif22 tmmk22 tmpr22 intm50 tmif50 tmmk50 tmpr50 intm51 tmif51 tmmk51 tmpr51 intm52 tmif52 tmmk52 tmpr52 intwti wtiif wtimk wtipr intwt wtif wtmk wtpr intwdt wdtif wdtmk wdtpr intad adif admk adpr intcsi30 csiif30 csimk30 csipr30 intser0 serif0 sermk0 serpr0 intsr0 srif0 srmk0 srpr0 intst0 stif0 stmk0 stpr0 intce ceif cemk cepr intcr rrf crmk crpr intct0 ctif0 ctmk0 ctpr0 intct1 ctif1 ctmk1 ctpr1 intwe weif wemk wepr intcsi31 csiif31 csimk31 csipr31 356 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 (1) interrupt request flag registers (if0l, if0h, if1l) the interrupt request flag is set to 1 when the corresponding interrupt request is generated. it is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l, if0h, and if1l are set with a 1-bit or 8-bit memory manipulation instruction. if if0l and if0h are used as a 16-bit register if0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to 00h. figure 20-2: interrupt request flag register format cautions: 1. wdtif flag is r/w enabled only when the watchdog timer is used as an interval timer. if used in the watchdog timer mode 1, set wdtif flag to 0. 2. set always 0 in if1l bit 4. symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w if0l pif1 pif0 tmif22 tmif21 tmif20 ovfif adif wdtif ffe0h 00h r/w if0h srif0 serif0 csiif30 ctif1 ctif0 crif ceif pif2 ffe1h 00h r/w if1l csiif31 wtif wtiif 0 tmif52 tmif51 tmif50 stif0 ffe2h 00h r/w xxifx interrupt request flag 0 no interrupt request signal 1 interrupt request signal is generated; interrupt request state 357 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flag is used to enable/disable the corresponding maskable interrupt service. mk0l, mk0h, and mk1l are set with a 1-bit or 8-bit memory manipulation instruction. if mk0l and mk0h are used as a 16-bit register mk0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to ffh. figure 20-3: interrupt mask flag register format cautions: 1. if wdtmk flag is read when the watchdog timer is used as a non-maskable interrupt, wdtmk value becomes undefined. 2. set always 1 in mk1l bit 4. symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w mk0l pmk1 pmk0 tmmk22 tmmk21 tmmk20 ovfmk admk wdtmk ffe4h ffh r/w mk0h srmk0 sermk0 csimk30 ctmk1 ctmk0 crmk cemk pmk2 ffe5h ffh r/w mk1l csimk31 wtmk wtimk 1 tmmk52 tmmk51 tmmk50 stmk0 ffe6h ffh r/w xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled 358 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 (3) priority specify flag registers (pr0l, pr0h, pr1l) the priority specify flag is used to set the corresponding maskable interrupt priority orders. pr0l, pr0h, and pr1l are set with a 1-bit or 8-bit memory manipulation instruction. if pr0l and pr0h are used as a 16-bit register pr0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to ffh. figure 20-4: priority specify flag register format cautions: 1. the wdtpr flag is only valid, if the watchdog timer is used as interval timer. if the non-maskable interrupt of the watchdog timer is used, set wdtpr to 1. 2. set always 1 in pr1l bit 4. symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w pr0l ppr1 ppr0 tmpr22 tmpr21 tmpr20 ovfpr adpr wdtpr ffe8h ffh r/w pr0h srpr0 serpr0 csipr30 ctpr1 ctpr0 crpr cepr ppr2 ffe9h ffh r/w pr1l csipr31 wtpr wtipr 1 tmpr52 tmpr51 tmpr50 stpr0 ffeah ffh r/w xxprx priority level selection 0 high priority level 1 low priority level 359 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 (4) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) egp and egn specify the valid edge to be detected on pins p00 to p02. egp and egn can be read or written to with a 1-bit or 8-bit memory manipulation instruction. these registers are set to 00h when the reset signal is output. figure 20-5: formats of external interrupt rising edge enable register and external interrupt falling edge enable register symbol76543210addressafter resetr/w egp 0 0 0 0 0 egp2 egp1 egp0 ff48h 00h r/w symbol76543210addressafter resetr/w egn 0 0 0 0 0 egn2 egn1 egn0 ff49h 00h r/w egpn egnn valid edge of intpn pin (n = 0 - 2) 0 0 interrupt disable 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges 360 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 (5) program status word (psw) the program status word is a register to hold the instruction execution result and the current status for interrupt request. the ie flag to set maskable interrupts (enable/disable) and the isp flag to control multiple interrupt servicing are mapped. besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruc- tion and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged, and when the brk instruction is executed, the contents of psw automatically is saved onto the stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged contents of the priority specify flag of the acknowledged interrupt are transferred to the isp flag. the acknowl- edged contents of psw is also saved onto the stack with the push psw instruction. it is retrieved from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 20-6: program status word format symbol76543210after resetr/w psw ie z rbs1 ac rbs0 0 isp cy 02h r/w isp priority of interrupt currently being received 0 high-priority interrupt servicing (low-priority interrupt disable) 1 interrupt request not acknowledged or low-priority interrupt servicing (all-maskable interrupts enable) ie interrupt request acknowledge enable/disable 0 disable 1enable 361 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 20.4 interrupt servicing operations 20.4.1 non-maskable interrupt request acknowledge operation a non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. it does not undergo interrupt priority control and has highest priority over all other interrupts. if a non-maskable interrupt request is acknowledged, psw and pc are pushed on the stack. the ie and isp flags are reset to 0, and the vector table contents are loaded into pc. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servic- ing program is acknowledged after the current execution of the non-maskable interrupt servicing pro- gram is terminated (following reti instruction execution) and one main routine instruction is executed. if a new non-maskable interrupt request is generated twice or more during a non-maskable interrupt service program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt service program execution. figure 20-7: flowchart from non-maskable interrupt generation to acknowledge remark: wdtm : watchdog timer mode register wdt : watchdog timer wdt = 1 (with watchdog timer mode selected)? overflow in wdt? wdt = 0 (with non-maskable interrupt selected)? interrupt request generation wdt interrupt servicing? interrupt control register unaccessed? interrupt service start interrupt request held pending reset processing interval timer start no ye s ye s no ye s no ye s no ye s no 362 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 figure 20-8: non-maskable interrupt request acknowledge timing remark: wdtif : watchdog timer interrupt request flag figure 20-9: non-maskable interrupt request acknowledge operation (a) if a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution instruction instr uction cpu instruction wdtif psw and pc save, jump to interrupt servicing interrupt sevicing program nmi request nmi request 1 instruction execution main routine nmi request reserve reserved nmi request processing nmi request nmi request 1 instruction execution main routine reserved although two or more nmi requests have been generated, only one request has been acknowledged. nmi request reserved 363 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 20.4.2 maskable interrupt request acknowledge operation a maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (mk) flag is cleared to 0. a vectored interrupt request is acknowledged in an interrupt enable state (with ie flag set to 1). however, a low-priority interrupt request is not acknowledged during high-priority interrupt service (with isp flag reset to 0). wait times from maskable interrupt request generation to interrupt servicing are as follows. note: if an interrupt request is generated just before a divide instruction, the wait time is maximized. remark: 1 clock: 1/ f cpu (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority with the priority specify flag is acknowledged first. if two or more requests are specified for the same priority with the priority specify flag, the interrupt request with the higher default priority is acknowledged first. any reserved interrupt requests are acknowledged when they become acknowledgeable. figure 20-10 on page 364 shows interrupt request acknowledge algorithms. when a maskable interrupt request is acknowledged, the contents of program status word (psw) and program counter (pc) are saved in this order onto the stack. then, the ie flag is reset (to 0), and the value of the acknowledged interrupt priority specify flag is transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into pc and the program will branch accordingly. return from the interrupt is possible with the reti instruction. table 20-3: times from maskable interrupt request generation to interrupt service minimum time maximum time note when xxprx = 0 7 clocks 32 clocks when xxprx = 1 8 clocks 33 clocks 364 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 figure 20-10: interrupt request acknowledge processing algorithm remark: xxif : interrupt request flag xxmk : interrupt mask flag xxpr : priority specify flag ie : flag to control maskable interrupt request acknowledge isp : flag to indicate the priority of interrupt being serviced (0 = an interrupt with higher priority is being serviced, 1 = interrupt request is not acknowledged or an interrupt with lower priority is being serviced) start xxif = 1? xxmk = 0? xxpr = 0? any simultaneously generated xxpr = 0 interrupts? ie = 1? isp = 1? vectored interrupt servicing interrupt request reserve any high- priority interrupt among simultaneously generated xxpr = 0 interrupts? ie = 1? yes (high priority) yes no ye s no no no yes (interrupt request generation) no ye s no (low priority) yes yes no ye s ye s no no any simultaneously generated high-priority interrupts? interrupt request reserve interrupt request reserve interrupt request reserve vectored interrupt servicing interrupt request reserve interrupt request reserve interrupt request reserve 365 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 figure 20-11: interrupt request acknowledge timing (minimum time) remark: 1 clock: 1/ f cpu (f cpu : cpu clock) figure 20-12: interrupt request acknowledge timing (maximum time) remark: 1 clock: 1/ f cpu (f cpu : cpu clock) instruction instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 8 clocks 7 clocks cpu processing xxif (xxpr = 1) xxif (xxpr = 0) instruction divide instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 33 clocks 32 clocks cpu processing xxif (xxpr = 1) xxif (xxpr = 0) 25 clocks 366 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 20.4.3 software interrupt request acknowledge operation a software interrupt request is acknowledged by brk instruction execution. software interrupt cannot be disabled. if a software interrupt is acknowledged, the contents of program status word (psw) and program coun- ter (pc) are saved to stacks, in this order. then the ie flag is reset (to 0), and the contents of the vector tables (003eh and 003fh) are loaded into pc and the program branches accordingly. return from the software interrupt is possible with the retb instruction. caution: do not use the reti instruction for returning from the software interrupt. 20.4.4 multiple interrupt servicing a multiple interrupt service consists in acknowledging another interrupt during the execution of another interrupt routine. a multiple interrupt service is generated only in the interrupt request acknowledge enable state (ie = 1) (except non-maskable interrupt). as soon as an interrupt request is acknowledged, it enters the acknowledge disable state (ie = 0). therefore, in order to enable multiple interrupts, it is necessary to set the interrupt enable state by setting the ie flag (1) with the ei instruction during interrupt servicing. even in an interrupt enabled state, a multiple interrupt may not be enabled. however, it is controlled according to the interrupt priority. there are two priorities, the default priority and the programmable pri- ority. the multiple interrupt is controlled by the programmable priority control. if an interrupt request with the same or higher priority than that of the interrupt being serviced is gener- ated, it is acknowledged as a multiple interrupt. in the case of an interrupt with a priority lower than that of the interrupt being processed, it is not acknowledged as a multiple interrupt. an interrupt request not acknowledged as a multiple interrupt due to interrupt disable or a low priority is reserved and acknowledged following one instruction execution of the main processing after the com- pletion of the interrupt being serviced. during non-maskable interrupt servicing, multiple interrupts are not enabled. table 20-4 on page 367 shows an interrupt request enabled for multiple interrupt during interrupt servic- ing, and figure 20-13 on page 368 shows multiple interrupt examples. 367 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 remarks: 1. e : multiple interrupt enable 2. d : multiple interrupt disable 3. isp and ie are the flags contained in psw isp = 0 : an interrupt with higher priority is being serviced isp = 1 : an interrupt request is not accepted or an interrupt with lower priority is being serviced ie = 0 : interrupt request acknowledge is disabled ie = 1 : interrupt request acknowledge is enabled 4. xxpr is a flag contained in pr0l, pr0h, and pril xxpr = 0 : higher priority level xxpr = 1 : lower priority level table 20-4: interrupt request enabled for multiple interrupt during interrupt servicing maskable interrupt request non-maskable interrupt request maskable interrupt request xxpr = 0 xxpr = 1 interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 non-maskable interrupt d d d d d maskable interrupt isp = 0 e e d d d isp = 1 e e d e d software interrupt e e d e d 368 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 figure 20-13: multiple interrupt example (1/2) (a) example 1. two multiple interrupts generated during interrupt intxx servicing, two interrupt requests, intyy and intzz are acknowledged, and a mul- tiple interrupt is generated. an ei instruction is issued before each interrupt request acknowledge, and the interrupt request acknowledge enable state is set. (b) example 2. multiple interrupt is not generated by priority control the interrupt request intyy generated during interrupt intxx servicing is not acknowledged because the interrupt priority is lower than that of intxx, and a multiple interrupt is not generated. intyy request is retained and acknowledged after execution of 1 instruction execution of the main processing. remark: pr = 0 : higher priority level pr = 1 : lower priority level ie = 0 : interrupt request acknowledge disable main processing ei intxx (pr = 1) intyy (pr = 0) ie = 0 ei reti intxx servicing intzz (pr = 0) ie = 0 ei reti intyy servicing ie = 0 reti intzz servicing main processing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 1) ei ie = 0 ei reti reti 369 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 figure 20-13: multiple interrupt example (2/2) (c) example 3. a multiple interrupt is not generated because interrupts are not enabled because interrupts are not enabled in interrupt intxx servicing (an ei instruction is not issued), inter- rupt request intyy is not acknowledged, and a multiple interrupt is not generated. the intyy request is reserved and acknowledged after 1 instruction execution of the main processing. remark: pr = 0 : higher priority level ie = 0 : interrupt request acknowledge disable main processing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 0) ie = 0 reti reti ei 370 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 20.4.5 interrupt request reserve some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interrupt request is generated during the execution. the following list shows such instructions (interrupt request reserve instruction). mov psw, #byte mov a, psw mov psw, a mov1 psw.bit, cy mov1 cy, psw.bit and1 cy, psw.bit or1 cy, psw.bit xor cy, psw.bit set1/clr1 psw.bit retb reti push psw pop psw bt psw.bit, $addr16 bf psw.bit, $addr16 btclr psw.bit, $addr16 ei di manipulate instructions: for if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, pr1l, egp, egn caution: brk instruction is not an interrupt request reserve instruction described above. however, in a software interrupt started by the execution of brk instruction, the ie flag is cleared to 0. therefore, interrupt requests are not acknowledged even when a maskable interrupt request is issued during the execution of the brk instruction. however, non-maskable interrupt requests are acknowledged. 371 chapter 20 interrupt functions user ? s manual u16504ee1v1ud00 figure 20-14 shows the interrupt request hold timing. figure 20-14: interrupt request hold remarks: 1. instruction n: instruction that holds interrupts requests 2. instruction m: instructions other than interrupt request pending instruction 3. the xxpr (priority level) values do not affect the operation of xxif (interrupt request). cpu processing xxif instruction n instruction m save psw and pc, jump to interrupt service interrupt service program 372 user ? s manual u16504ee1v1ud00 [memo] 373 user ? s manual u16504ee1v1ud00 chapter 21 standby function 21.1 standby function and configuration 21.1.1 standby function the standby function is designed to decrease the power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode is intended to stop the cpu operation clock. system clock oscillator continues oscillation. in this mode, current consumption cannot be decreased as much as in the stop mode. the halt mode is capable of restart imme- diately upon interrupt request and to carry out intermittent operations such as watch applications. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the main system clock oscil- lator stops and the whole system stops. cpu current consumption can be considerably decreased. data memory low-voltage hold is possible. thus, the stop mode is effective to hold data memory contents with ultra-low current consumption. because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. however, because a wait time is necessary to secure an oscillation stabilization time after the stop mode is cleared, select the halt mode if it is necessary to start processing immediately upon interrupt request. in any mode, all the contents of the register, flag, and data memory just before entering the standby mode are held. the input/output port output latch and output buffer status are also held. cautions: 1. when proceeding to the stop mode, be sure to stop the peripheral hardware operation and execute the stop instruction afterwards. 2. the following sequence is recommended for power consumption reduction of the a/d converter when the standby function is used: first clear bit 7 (adcs1) of adm1 to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction. 374 chapter 21 standby function user ? s manual u16504ee1v1ud00 21.1.2 standby function control register a wait time after the stop mode is cleared upon interrupt request till the oscillation stabilizes is control- led with the oscillation stabilization time select register (osts). osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, it takes 2 17 /f x until the stop mode is cleared by reset input. figure 21-1: oscillation stabilization time select register format caution: the wait time after stop mode clear does not include the time (see ? a ? in the figure 21-2 below) from stop mode clear to clock oscillation start, regardless of clearance by reset input or by interrupt generation. figure 21-2: standby timing remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operating at f x = 8.00 mhz symbol76543210addressafter resetr/w osts00000osts2osts1osts0fffah04hr/w osts2 osts1 osts0 selection of oscillation stabilization time when stop mode is released 000 2 12 /f x (512 s) 001 2 14 /f x (2 ms) 010 2 15 /f x (4.1 ms) 111 2 16 /f x (8.9 ms) 100 2 17 /f x (16.38 ms) other than above setting prohibited stop mode clear x1 pin voltage waveform v ss a 375 chapter 21 standby function user ? s manual u16504ee1v1ud00 21.2 standby function operations 21.2.1 halt mode (1) halt mode set and operating status the halt mode is set by executing the halt instruction. the operating status in the halt mode is described below. table 21-1: halt mode operating status halt mode setting halt execution during main system clock operation item clock generator main clock is oscillating / clock supply to the cpu stops cpu operation stops port (output latch) status before halt mode setting is held 16-bit timer (tm2) operable 8-bit timer event counter (tm50/tm51/tm52) operable watch timer operable watchdog timer operable a/d converter operation stops serial i/f (sio30, sio31) operable serial i/f (uart) operable can operation stops sound generator operable external interrupt (intp0 to intp2) operable lcd - c/d operable meter - c/d operable 376 chapter 21 standby function user ? s manual u16504ee1v1ud00 (2) halt mode clear the halt mode can be cleared with the following four types of sources. (a) clear upon unmasked interrupt request an unmasked interrupt request is used to clear the halt mode. if interrupt acknowledge is ena- bled, vectored interrupt service is carried out. if disabled, the next address instruction is executed. figure 21-3: halt mode clear upon interrupt generation remarks: 1. the broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. 2. wait time will be as follows: when vectored interrupt service is carried out : 8 to 9 clocks when vectored interrupt service is not carried out : 2to 3 clocks (b) clear upon non-maskable interrupt request the halt mode is cleared and vectored interrupt service is carried out whether interrupt acknowl- edge is enabled or disabled. halt instruction wait standby release signal operating mode clock halt mode wait oscillation operating mode 377 chapter 21 standby function user ? s manual u16504ee1v1ud00 (c) clear upon reset input as is the case with normal reset operation, a program is executed after branch to the reset vector address. figure 21-4: halt mode release by reset input remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operation at f x = 8.0 mhz remark: x: don ? t care table 21-2: operation after halt mode release release source mkxx prxx ie isp operation maskable interrupt request 0 0 0 x next address instruction execution 0 0 1 x interrupt service execution 0101 next address instruction execution 01x0 0 1 1 1 interrupt service execution 1 x x x halt mode hold non-maskable interrupt request - - x x interrupt service execution reset input - - x x reset processing halt instruction reset signal operating mode clock reset period halt mode oscillation oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 16.38 ms) 378 chapter 21 standby function user ? s manual u16504ee1v1ud00 21.2.2 stop mode (1) stop mode set and operating status the stop mode is set by executing the stop instruction. it can be set only with the main system clock. cautions: 1. when the stop mode is set, the x2 pin is internally connected to v dd via a pull- up resistor to minimize leakage current at the crystal oscillator. thus, do not use the stop mode in a system where an external clock is used for the main system clock. 2. if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction. after the wait time set using the oscillation stabilization time select register (osts), the operating mode is set. the operating status in the stop mode is described below. table 21-3: stop mode operating status stop mode setting stop execution during main system clock operation item clock generator main system clock stops oscillation cpu operation stops port (output latch) status before stop mode setting is held 16-bit timer (tm2) operation stops 8-bit timer/event counter (tm50, tm51) operable when ti50 or ti51 are selected as count clock 8-bit timer (tm52) operation stops watch timer operation stops watchdog timer operation stops a/d converter operation stops serial i/f (sio30, sio31) operable at external sck serial i/f (uart) operation stops can operation stops sound generator operation stops external interrupt (intp0 to intp2) operable lcd - c/d operation stops meter - c/d operation stops 379 chapter 21 standby function user ? s manual u16504ee1v1ud00 (2) stop mode release the stop mode can be cleared with the following three types of sources. (a) release by unmasked interrupt request an unmasked interrupt request is used to release the stop mode. if interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. if interrupt acknowledge is disabled, the next address instruction is executed. figure 21-5: stop mode release by interrupt generation remark: the broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. stop instruction wait (time set by osts) oscillation stabilization wait status operating mode oscillation operating mode stop mode oscillation stop oscillation standby release signal clock 380 chapter 21 standby function user ? s manual u16504ee1v1ud00 (b) release by reset input the stop mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. figure 21-6: release by stop mode reset input remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operation at f x = 8.0 mhz remark: x: don ? t care table 21-4: operation after stop mode release release source mkxx prxx ie isp operation maskable interrupt request 0 0 0 x next address instruction execution 0 0 1 x interrupt service execution 0101 next address instruction execution 01x0 0 1 1 1 interrupt service execution 1 x x x stop mode hold reset input - - x x reset processing reset signal operating mode clock reset period st op mode oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 16.38 ms) stop instruction oscillation 381 user ? s manual u16504ee1v1ud00 chapter 22 reset function 22.1 reset function the following two operations are available to generate the reset signal. external reset input with reset pin internal reset by watchdog timer overrun time detection external reset and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status as shown in table 23-1. each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. when a high level is input to the reset input, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ). the reset applied by watchdog timer overflow is auto- matically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ) (see figure 22-2, ? timing of reset input by reset input, ? on page 382, figure 22-3, ? tim- ing of reset due to watchdog timer overflow, ? on page 382, and figure 22-4, ? timing of reset input in stop mode by reset input, ? on page 383). cautions: 1. for an external reset, apply a low level for 10 s or more to the reset pin. 2. during reset the main system clock oscillation remains stopped but the sub- system clock oscillation continues. 3. when the stop mode is cleared by reset, the stop mode contents are held dur- ing reset. however, the port pin becomes high-impedance. figure 22-1: block diagram of reset function reset count clock reset control circuit watchdog timer stop overflow reset signal interrupt function 382 chapter 22 reset function user ? s manual u16504ee1v1ud00 figure 22-2: timing of reset input by reset input figure 22-3: timing of reset due to watchdog timer overflow reset internal reset signal port pin delay delay high impedance x1 normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 normal operation watchdog timer overflow internal reset signal port pin high impedance reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) 383 chapter 22 reset function user ? s manual u16504ee1v1ud00 figure 22-4: timing of reset input in stop mode by reset input table 22-1: hardware status after reset (1/3) hardware status after reset program counter (pc) note 1 the contents of reset vector tables (0000h and 0001h) are set stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note 2 general register undefined note 2 lcd display data memory note 4 port (output latch) ports 0, 2, 3, 4, 5, 6, 8, 9 (p0, p2, p3, p4, p5,p6, p8, p9) 00h port mode register (pm0, pm2, pm3, pm4, pm5, pm6, pm8, pm9) ffh pull-up resistor option register (pu0, pu3, pu4, pu6, pu8, pu9) 00h port function selection (pf3, pf4, pf8, pf9) 00h processor clock control register (pcc) 04h memory size switching register (ims) cfh internal expansion ram size switching register (ixs) note 3 oscillation stabilization time select register (osts) 04h 16-bit timer/event counter 2 timer register (tm2) 00h capture control register (cr20, cr21, cr22) 00h prescaler mode register (prm2) 00h mode control register (tmc2) 00h notes: 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware sta- tuses become undefined. all other hardware statuses remains unchanged after reset. 2. the post-reset status is held in the standby mode. 3. the value after reset depends on the product (see table 23-4, ? values when the internal expansion ram size switching register is reset, ? on page 389) 4. reset clears the lcd display data memory to 00h. reset internal reset signal port pin high impedance x1 stop instruction execution normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) stop status (oscillation stop) delay delay 384 chapter 22 reset function user ? s manual u16504ee1v1ud00 8-bit timer/event counters 50, 51 and 52 timer register (tm50, tm51, tm52) 00h compare register (cr50, cr51, cr52) 00h clock select register (tcl50, tcl51, tcl52) 00h mode control register (tmc50, tmc51, tmc52) 00h watch timer mode register (wtm) 00h watchdog timer clock selection register (wdcs) 00h mode register (wdtm) 00h pcl clock output clock output selection register (cks) 00h sound generator control register (sgcr) 00h amplitude control (sgam) 00h buzzer control (sgbc) 00h serial interface operating mode register (csim30, csim31) 00h shift register (sio30, sio31) 00h serial interface switch register (sioswi) 00h asynchronous mode register (asim0) 00h asynchronous status register (asis0) 00h baudrate generator control register (brgl0) 00h transmit shift register (txs0) ffh receive buffer register (rxb0) a/d converter mode register (adm1) 00h conversion result register (adcr1) 00h input select register (ads1) 00h power fail comparator mode register (pfm) 00h power fail comparator transload register (pft) 00h lcd-controller/driver mode register (lcdm) 00h control register (lcdc) 00h interrupt request flag register (if0l, if0h, if1l) 00h mask flag register (mk0l, mk0h, mk1l) ffh priority specify flag register (pr0l, pr0h, pr1l) ffh external interrupt rising edge register (egp) 00h external interrupt falling edge register (egn) 00h flash self-programming flash self-programming mode control register (flpmc) 08h self-programming and oscillation control reg- ister (spoc) 08h table 22-1: hardware status after reset (2/3) hardware status after reset 385 chapter 22 reset function user ? s manual u16504ee1v1ud00 can control register (canc) 01h transmit control register (tcr) 00h receive message register (rmes) 00h redefinition register (redef) 00h error status register (canes) 00h transmit error counter register (tec) 00h receive error counter register (rec) 00h message count register (mcnt) 00h bit rate prescaler register (brprs) 3fh synchronous control register (sync0) 18h synchronous control register (sync1) 0eh mark control register (maskc) 00h counter register (smcnt) 00h pwm timer control register (mcntc) 00h stepper motor controller/driver (instrument c10) port mode control register 00h 8 bit compare register (mcmp10, mcmp11, mcmp20, mcmp21, mcmp30, mcmp31, mcmp40, mcmp41) 00h compare control register (mcmpc1, mcmpc2, mcmpc3, mcmpc4) 00h meter controller/driver clock switch register (smswi) 00h table 22-1: hardware status after reset (3/3) hardware status after reset 386 user ? s manual u16504ee1v1ud00 [memo] 387 user ? s manual u16504ee1v1ud00 chapter 23 pd78f0828a and memory definition the flash memory versions of the pd780828a subseries includes the pd78f0828a. the pd78f0828a replaces the internal mask rom of the pd780828a with flash memory to which a program can be written, deleted and overwritten while mounted on the pcb. table 23-1 lists the differ- ences among the pd78f0828a and the mask rom versions. caution: flash memory versions and mask rom versions differ in their noise tolerance and noise emission. if replacing flash memory versions with mask rom versions when changing from test production to mass production, be sure to perform sufficient eval- uation with cs versions (not es versions) of mask rom versions. table 23-1: differences among pd78f0828a and mask rom versions item pd78f0828a mask rom versions ic pin none available v pp pin available none electrical characteristics please refer to chapter 25 ? electrical specifica- tions ? on page 411 of this document. 388 chapter 23 pd78f0828a and memory definition user ? s manual u16504ee1v1ud00 23.1 memory size switching register (ims) this register specifies the internal memory size by using the memory size switching register (ims), so that the same memory map as on the mask rom version can be achieved by using the flash device. ims is set with an 8-bit memory manipulation instruction. reset input sets this register to cfh. caution: when later on a mask device of the pd780828a subseries is selected, be sure to set the value for this mask device as specified in table 23-2 to ims. other settings are prohibited. figure 23-1: memory size switching register format notes: 1. the values to be set after reset depend on the product (see table 23-2). 2. even if the flash version has a memory size of 59.5 k flash memory, the register has to be set to a flash memory size of 60 k. symbol76543210addressafter resetr/w ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 fff0h cfh r/w rom3 rom2 rom1 rom0 internal rom size selection 1000 32 k bytes 1100 48 k bytes 1111 60 k bytes other than above setting prohibited ram2 ram1 ram0 internal high-speed ram size selection 1 1 0 1024 bytes other than above setting prohibited table 23-2: values to be set after reset for the memory size switching register part number reset value pd780824b c8h pd780826b cch pd780828b cfh pd78f0828b cfh ? ? ? ? 389 chapter 23 pd78f0828a and memory definition user ? s manual u16504ee1v1ud00 23.2 internal expansion ram size switching register the pd78f0828a allows users to define its internal extension ram size by using the internal expansion ram size switching register (ixs), so that the same memory mapping as that of a mask rom version with a different internal expansion ram is possible. the ixs is set by an 8-bit memory manipulation instruction. reset signal input sets ixs to the value indicated in table 23-4. caution: when later on a mask device of the pd780828a subseries is selected, be sure to set the value for this mask device as specified in table 23-2 to ims. other settings are prohibited. figure 23-2: internal expansion ram size switching register format notes: 1. the values after reset depend on the product (see table 23-4). 2. the value which is set in the ixs that has the identical memory map to the mask rom ver- sions is given in table 23-3. symbol76543210addressafter resetr/w ixs0000ixram3ixram2ixram1ixram0fff4h note 1 r/w ixram3 ixram2 ixram1 ixram0 internal expansion ram capacity selection 1011 480 bytes 1000 2016 bytes other than above setting prohibited table 23-3: examples of internal expansion ram size switching register settings relevant mask rom version ixs setting pd780824a 0bh pd780826a 0bh pd780828a 08h pd78f0828a 08h table 23-4: values when the internal expansion ram size switching register is reset part number reset value pd780824a 0ch pd780826a 0ch pd780828a 0ch pd78f0828a 08h ? ? ? 390 chapter 23 pd78f0828a and memory definition user ? s manual u16504ee1v1ud00 23.3 self-programming and oscillation control register the pd78f0828a allows users to reduce the power consumption in halt mode by a selection of the clock supply of the flash memory. the spoc register is set with an 8-bit memory manipulation instruction. reset signal input sets spoc to 08h. figure 23-3: self-programming and oscillation control register format symbol76543210addressafter resetr/w spoc000000hcsel1hcsel0ff51h08hr/w hcsel1 hcsel0 halt mode clock select 00 f x /2 4 (500 khz) 01 f x /2 5 (250 khz) 10 f x /2 6 (125 khz) 11 f x /2 7 (62.5 khz) 391 chapter 23 pd78f0828a and memory definition user ? s manual u16504ee1v1ud00 23.4 flash memory programming with flash programmer on-board writing of flash memory (with device mounted on target system) is supported. on-board writing is done after connecting a dedicated flash writer to the host machine and the target system. moreover, writing to flash memory can also be performed using a flash memory writing adapter con- nected to flash programmer. 23.4.1 selection of transmission method writing to flash memory is performed using flash programmer and serial communication. select the transmission method for writing from table 23-5. for the selection of the transmission method, a format like the one shown in figure 23-4 is used. the transmission methods are selected with the v pp pulse numbers shown in table 23-5. cautions: 1. be sure to select the number of v pp pulses shown in table 23-5 for the transmis- sion method. 2. if performing write operations to flash memory with the uart transmission method, set the main system clock oscillation frequency to 3 mhz or higher. figure 23-4: transmission method selection format 23.4.2 initialization of the programming mode when v pp reaches up to 10 v with reset terminal activated, on-board programming mode becomes available. after release of reset , the programming mode is selected by the number of v pp pulses. table 23-5: transmission method list transmission method number of channels pin used number of v pp pulses 3-wire serial i/o (sio30) 1 si30/p37, so30/p36, sck30/p35 0 3-wire serial i/o (sio30) with handshake 1 si30/p37, so30/p36, sck30/p35, handshake/p34 3 uart 1 rxd0/p62, txd0/p63 8 10 v v pp reset v dd v ss v dd v ss v pp pulses flash write mode 392 chapter 23 pd78f0828a and memory definition user ? s manual u16504ee1v1ud00 23.4.3 flash memory programming function flash memory writing is performed through command and data transmit/receive operations using the selected transmission method. the main functions are listed in table 23-6. table 23-6: main functions of flash memory programming function description reset detects write stop and transmission synchronization chip verify compares the entire memory contents and input data chip internal verify compares the entire memory contents internally chip blank check checks the deletion status of the entire flash memory high-speed write performs writing to the flash memory according to the write start address and the number of write data (bytes) continuous write performs successive write operations using the data input with high- speed write operation chip pre-write performs the write operation with 00h to the entire flash memory area verify compares the entire flash area contents and input data area internal verify compares the entire flash area contents internally area erase erases the entire flash area area write back performs the write back function after the erase of the flash area area blank check checks the deletion status of the entire flash area area pre-write performs the write operation with 00h to the entire flash area oscillation frequency setting inputs the resonator oscillation frequency information erase time setting defines the flash memory erase time baudrate setting sets the transmission rate when the uart method is used write back time setting defines the flash memory write back time silicon signature read outputs the device name, memory capacity, and device block information 393 chapter 23 pd78f0828a and memory definition user ? s manual u16504ee1v1ud00 23.4.4 flash programmer connection connection of flash programmer and pd78f0828a differs depending on communication method (3-wire serial i/o, uart). each case of connection shows in figures 23-5, 23-6 and 23-7. figure 23-5: connection of using the 3-wire sio30 method figure 23-6: connection of using the 3-wire sio30 method with handshake v pp v dd reset sck so si gnd v pp v dd reset sck30 si30 so30 v ss flash programmer pd78f0828a clk x1 v pp v dd reset sck so si gnd v pp v dd reset sck30 si30 so30 v ss flash programmer pd78f0828a clk x1 reserved p34 394 chapter 23 pd78f0828a and memory definition user ? s manual u16504ee1v1ud00 figure 23-7: connection of using the uart method v pp : programming voltage applied from the on-board programming tool. reset : a reset is generated and the device is set to the on-board programming mode. system clock : the cpu clock for the device clk may be supplied by the on-board program tool. clk, x1 : alternatively the crystal or ceramic oscillator on the target h/w can be used in the on-board programming mode. the external system clock has to be connected with the x1 pin on the device. v dd : the power supply for the device may be supplied by the on-board program tool. alternatively the power supply on the target h/w can be used in the on-board programming mode. gnd : ground level v ss . sck30 : serial clock generated by the on-board programming tool. si30 : serial data sent by the on-board programming tool. so30 : serial data sent by the device. rxd : serial data sent by the on-board programming tool. txd : serial data sent by the device. hs : handshake line. 23.4.5 flash programming precautions please make sure that the signals used by the on-board programming tool do not conflict with other devices on the target h/w. a read functionality is not supported because of software protection. only a verify operation of the whole flash eprom is supported. in verify mode data from start address to final address has to be supplied by the programming tool. the device compares each data with on-chip flash content and replies with a signal for o.k. or not o.k. v pp v dd reset so si gnd v pp v dd reset rxd0 txd0 v ss flash programmer pd78f0828a clk x1 395 chapter 23 pd78f0828a and memory definition user ? s manual u16504ee1v1ud00 23.5 flash self-programming control the pd78f0828a provides the secure self-programming with real-time support. further details are provided in an application note (u14995e). 23.5.1 flash self-programming mode control register the flash programming mode control register allows to enable/disable the self-programming mode of the pd78f0828a. the flpmc register is set with an 8-bit memory manipulation instruction. reset input sets flpmc to 08h. figure 23-8: flash self-programming mode control register format remark: the bit v pp is a read-only flag. symbol76543210addressafter resetr/w flpmc00001 v pp 0 flspm0 ff50h 08h r/w v pp programming voltage detected 0no 1yes flspm0 self-programming mode selection 0 normal operation mode 1 self-programming mode 396 user ? s manual u16504ee1v1ud00 [memo] 397 user ? s manual u16504ee1v1ud00 chapter 24 instruction set this chapter describes each instruction set of the pd780828a subseries as list table. for details of its operation and operation code, refer to the separate document ? 78k/0 series user ? s manual - instruction (u12326e) . ? 24.1 legends used in operation list 24.1.1 operand identifiers and description methods operands are described in ? operand ? column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be described as they are. each symbol has the following meaning. # : immediate data specification ! : absolute address specification $ : relative address specification [ ] : indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $, and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. note: addresses from ffd0h to ffdfh cannot be accessed with these operands. remark: for special-function register symbols, refer to table 3-5, ? special function register list, ? on page 67 . table 24-1: operand identifiers and description methods identifier description method r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special-function register symbol note sfrp special-function register symbol (16-bit manipulatable register even addresses only) note saddr fe20h-ff1fh immediate data or labels saddrp fe20h-ff1fh immediate data or labels (even address only) addr16 0000h-ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h-0fffh immediate data or labels addr5 0040h-007fh immediate data or labels (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 398 chapter 24 instruction set user ? s manual u16504ee1v1ud00 24.1.2 description of ? operation ? column a : a register; 8-bit accumulator x:x register b:b register c : c register d : d register e:e register h : h register l : l register ax : ax register pair; 16-bit accumulator bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag rbs : register bank select flag ie : interrupt request enable flag nmis : non-maskable interrupt servicing flag ( ) : memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ?? : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 25.1.3 description of ? flag operation ? column (blank) : not affected 0 : cleared to 0 1 : set to 1 x : set/cleared according to the result r : previously saved value is restored 399 chapter 24 instruction set user ? s manual u16504ee1v1ud00 24.2 operation list table 24-2: operation list (1/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy 8-bit data transfer mov r, #byte 2 4 - r ? ? ? ? ? ? ? ? ? ? r = a ? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 400 chapter 24 instruction set user ? s manual u16504ee1v1ud00 16-bit data transfer movw rp, #word 3 6 - rp rp 8-bit operation add a, #byte 2 4 - a, cy table 24-2: operation list (2/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ? r = a ? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 401 chapter 24 instruction set user ? s manual u16504ee1v1ud00 8-bit operation sub a, #byte 2 4 - a, cy table 24-2: operation list (3/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ? r = a ? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 402 chapter 24 instruction set user ? s manual u16504ee1v1ud00 8-bit operation or a, #byte 2 4 - a ? word c table 24-2: operation list (4/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ? r = a ? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 403 chapter 24 instruction set user ? s manual u16504ee1v1ud00 increment/ decrement inc r12-r ? 1 ? 1 ? 1 ? 1 ? 0 ? 0 , (hl) 7 ? 4 ? 0 , (hl) 3 ? 0 ? 4 rol4 [hl] a 3 ? 0 ? 4 , (hl) 3 ? 0 ? 0 , (hl) 7 ? 4 ? 0 bcd adjust adjba 2 4 - decimal adjust accumulator after addition table 24-2: operation list (5/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ? r = a ? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 404 chapter 24 instruction set user ? s manual u16504ee1v1ud00 bit manipulate or1 cy, saddr.bit 3 6 7 cy table 24-2: operation list (6/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ? r = a ? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 405 chapter 24 instruction set user ? s manual u16504ee1v1ud00 call/return call !addr16 3 7 - (sp ? 1) ? 2) ? 2 callf !addr11 2 5 - (sp ? 1) ? 2) ? 11 ? 0 ? 2 callt [addr5] 1 6 - (sp ? 1) ? 2) ? 2 brk 1 6 - (sp ? 1) ? 2) ? 3) ? 3, ie ? 1) ? 1 rp 1 4 - (sp ? 1) ? 2) ? 2 pop psw 1 2 - psw table 24-2: operation list (7/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ? r = a ? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 406 chapter 24 instruction set user ? s manual u16504ee1v1ud00 condi- tional branch bt saddr.bit, $addr16 3 8 9 pc ? 1, then pc ? 1, then pc ? 1, then pc table 24-2: operation list (8/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ? r = a ? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 407 chapter 24 instruction set user ? s manual u16504ee1v1ud00 24.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note: except r = a table 24-3: 8-bit instructions 2nd operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none 1st operand a add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc rmov mov add addc sub subc and or xor cmp inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] [hl + b] [hl + c] mov x mulu c divu w 408 chapter 24 instruction set user ? s manual u16504ee1v1ud00 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw note: only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr table 24-4: 16-bit instructions 2nd operand #word ax rp note sfrp saddrp !addr16 sp none 1st operand ax addw subw cmpw movw xchw movw movw movw movw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw table 24-5: bit manipulation instructions 2nd operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none 1st operand a.bit mov1 bt bf btclr set1 clr1 sfr.bit mov1 bt bf btclr set1 clr1 saddr.bit mov1 bt bf btclr set1 clr1 psw.bit mov1 bt bf btclr set1 clr1 [hl].bit mov1 bt bf btclr set1 clr1 cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 set1 clr1 not1 409 chapter 24 instruction set user ? s manual u16504ee1v1ud00 (4) call/instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop table 24-6: call/instructions/branch instructions 2nd operand ax !addr16 !addr11 [addr5] $addr16 1st operand basic instruction br call br callf callt br bc bnc bz bnz compound instruction bt bf btclr dbnz 410 user ? s manual u16504ee1v1ud00 [memo] 411 user ? s manual u16504ee1v1ud00 chapter 25 electrical specifications 25.1 absolute maximum ratings (1) pd780824a(a), pd780826a(a), pd780828a(a), pd78f0828a(a) (t a = 25 c) table 25-0: (1/2) parameter symbol conditions rating unit supply voltage v dd -0.3 to + 6.0 v v pp pd78f0828a(a) only -0.3 to + 11.0 av dd / av ref av dd = v dd -0.3 to v dd + 0.3 av ss -0.3 to + 0.3 smv dd smv dd = v dd , v dd = 5 v 412 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 note: effective value should be calculated as follows: [effective value] = [peak value] table 25-0: (2/2) parameter symbol conditions rating unit 413 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (2) pd780824a(a1), pd780826a(a1), pd780828a(a1) (t a = 25 c) these specifications are only target values and may not be satisfied by mass-produced products. note: effective value should be calculated as follows: [effective value] = [peak value] 414 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (3) pd780824a(a2), pd780826a(a2), pd780828a(a2) (t a = 25 c) these specifications are only target values and may not be satisfied by mass-produced products. note: effective value should be calculated as follows: [effective value] = [peak value] 415 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 25.2 capacitance (1) pd780824a(a), pd780826a(a), pd780828a(a), pd78f0828a(a) (t a = 25 c, v dd = v ss = 0 v) remark: the characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. (2) pd780824a(a1), pd780826a(a1), pd780828a(a1) (t a = 25 c, v dd = v ss = 0 v) these specifications are only target values and may not be satisfied by mass-produced products. remark: the characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. parameter symbol function min. typ. max. unit input capacitance c in f = 1 mhz other than measured pins: 0 v 15 pf input/output capacitance c io f = 1 mhz other than measured pins: 0 v p00 to p03, p34 to p37, p40 to p47, p61 to p65, p80 to p87, p90 to p97, ctxd 15 pf p60, p20 to p27, p50 to p57 30 pf parameter symbol function min. typ. max. unit input capacitance c in f = 1 mhz other than measured pins: 0 v 15 pf input/output capacitance c io f = 1 mhz other than measured pins: 0 v p00 to p03, p34 to p37, p40 to p47, p61 to p65, p80 to p87, p90 to p97, ctxd 15 pf p60, p20 to p27, p50 to p57 30 pf 416 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (3) pd780824a(a2), pd780826a(a2), pd780828a(a2) (t a = 25 c, v dd = v ss = 0 v) these specifications are only target values and may not be satisfied by mass-produced products. remark: the characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. parameter symbol function min. typ. max. unit input capacitance c in f = 1 mhz other than measured pins: 0 v 15 pf input/output capacitance c io f = 1 mhz other than measured pins: 0 v p00 to p03, p34 to p37, p40 to p47, p61 to p65, p80 to p87, p90 to p97, ctxd 15 pf p60, p20 to p27, p50 to p57 30 pf 417 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 25.3 main system clock oscillation circuit characteristics (1) pd780824a(a), pd780826a(a), pd780828a(a), pd78f0828a(a) (t a = -40 c to +85 c, v dd = 4.0 to 5.5 v) notes: 1. indicates only oscillation circuit characteristics. refer to ? ac characteristics ? for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. caution: when using the main system clock oscillation circuit, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. wiring should be as short as possible. wiring should not cross other signal lines. wiring should not be placed close to a varying high current. the potential of the oscillation circuit capacitor ground should always be the same as that of v ss . do not ground wiring to a ground pattern in which a high current flows. do not fetch a signal from the oscillation circuit. resonator recommended circuit parameter conditions min. typ. max. unit ceramic resonator oscillator frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz oscillation stabiliza- tion time note 2 after v dd reaches oscillator voltage range min. 4.0 v 10 ms crystal resonator oscillator frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz oscillation stabiliza- tion time note 2 after v dd reaches oscillator voltage range min. 4.0 v 10 ms external clock x1 input frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz x1 input high/low-level width (t xh , t xl ) v dd = 4.0 to 5.5 v 55 125 ns ic x2 x1 c2 c1 ic x2 x1 c2 c1 x2 x1 pd74hcu04 open 418 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (2) pd780824a(a1), pd780826a(a1), pd780828a(a1) (t a = -40 c to +110 c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. notes: 1. indicates only oscillation circuit characteristics. refer to ? ac characteristics ? for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. caution: when using the main system clock oscillation circuit, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. wiring should be as short as possible. wiring should not cross other signal lines. wiring should not be placed close to a varying high current. the potential of the oscillation circuit capacitor ground should always be the same as that of v ss . do not ground wiring to a ground pattern in which a high current flows. do not fetch a signal from the oscillation circuit. resonator recommended circuit parameter conditions min. typ. max. unit ceramic resonator oscillator frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz oscillation stabiliza- tion time note 2 after v dd reaches oscillator voltage range min. 4.0 v 10 ms crystal resonator oscillator frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz oscillation stabiliza- tion time note 2 after v dd reaches oscillator voltage range min. 4.0 v 10 ms external clock x1 input frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz x1 input high/low-level width (t xh , t xl ) v dd = 4.0 to 5.5 v 55 125 ns ic x2 x1 c2 c1 ic x2 x1 c2 c1 x2 x1 pd74hcu04 open 419 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (3) pd780824a(a2), pd780826a(a2), pd780828a(a2) (t a = -40 c to +125 c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. notes: 1. indicates only oscillation circuit characteristics. refer to ? ac characteristics ? for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. caution: when using the main system clock oscillation circuit, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. wiring should be as short as possible. wiring should not cross other signal lines. wiring should not be placed close to a varying high current. the potential of the oscillation circuit capacitor ground should always be the same as that of v ss . do not ground wiring to a ground pattern in which a high current flows. do not fetch a signal from the oscillation circuit. resonator recommended circuit parameter conditions min. typ. max. unit ceramic resonator oscillator frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz oscillation stabiliza- tion time note 2 after v dd reaches oscillator voltage range min. 4.0 v 10 ms crystal resonator oscillator frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz oscillation stabiliza- tion time note 2 after v dd reaches oscillator voltage range min. 4.0 v 10 ms external clock x1 input frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz x1 input high/low-level width (t xh , t xl ) v dd = 4.0 to 5.5 v 55 125 ns ic x2 x1 c2 c1 ic x2 x1 c2 c1 x2 x1 pd74hcu04 open 420 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 25.4 dc characteristics (1) pd780824a(a), pd780826a(a), pd780828a(a), pd78f0828a(a) (t a = -40 c to +85 c, v dd = 4.0 to 5.5 v) table 25-0: (1/2) parameter symbol conditions min. typ. max. unit high-level input voltage v ih1 p00 - p03, p10 - p14, p34 - p37, p40 - p47, p60 - p65, p80 - p87, p90 - p97, crxd 0.7 v dd v dd v v ih2 reset 0.8 v dd v dd v ih4 x1, x2 v dd - 0.5 v dd low-level input voltage v il1 p00 - p03, p10 - p14, p34 - p37, p40 - p47, p60 - p65, p80 - p87, p90 - p97, crxd 0 0.3 v dd v il2 reset 0.2 v dd v il4 x1, x2 0 0.4 high-level output voltage v oh1 p00 - p03, p34 - p37, p40 - p47, p60 - p67, p80 - p87, p90 - p97, ctxd v dd = 4.0 - 5.5 v i oh = -1 ma v dd - 1.0 v oh2 p20 - p27, p50 - p57 4.5 v ? ? ? ? 421 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 remark: the characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. parameter symbol conditions min. typ. max. unit high-level output leakage current i loh v out = v dd 3 a low-level output leakage current i lol v out = 0 v -3 software pull-up resistor r2 v in = 0 v 4.5 v ? table 25-0: (2/2) 422 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 pd780824a(a), pd780826a(a), pd780828a(a) pd78f0828a(a) notes: 1. current through v dd0 , v dd1 respectively through v ss0 , v ss1 . excluded is the current through the inside pull-up resistors, through av dd /av ref , the port current and the current for the lcd split resistors. 2. cpu is operable. the other peripherals like: can controller, stepper motor c/d, timer 2, serial interfaces, sound generator and a/d converter are stopped. 3. cpu and all peripherals (except for the a/d converter) are in operating mode and pcl output is f x . 4. cpu is in halt mode and all other peripherals (except watch timer) are stopped. 5. cpu is in halt mode, but the following peripherals are active: timer 2, all other timers, serial interfaces, and pcl output is f x . remark: f x : main system clock oscillation frequency. the typical values are with respect to t a = 25 c. parameter symbol test conditions min. typ. max. unit power supply current note 1 i dd1 f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 2 5.5 11 ma f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 3 9.5 19 i dd2 f x = 8 mhz, crystal/ceramic oscillation halt mode (pcc = 04h) note 4 0.45 0.9 f x = 8 mhz, crystal/ceramic oscillation halt mode (pcc = 04h) note 5 2.5 5 i dd5 stop mode 1 30 a parameter symbol test conditions min. typ. max. unit power supply current note 1 i dd1 f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 2 10.5 21 ma f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 3 16 32 i dd2 f x = 8 mhz, crystal/ceramic oscillation halt mode (pcc = 04h) note 4 0.6 1.2 f x = 8 mhz, crystal/ceramic oscillation halt mode (pcc = 04h) note 5 2.7 5.5 i dd5 stop mode 1 30 a 423 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 pd780824a(a), pd780826a(a), pd780828a(a), pd78f0828a(a) lcd c/d 1/3 bias method note: the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcd ). parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd 3.0 v dd v lcd split resistor r lcd 51545k ? 424 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (2) pd780824a(a1), pd780826a(a1), pd780828a(a1) (t a = -40 c to +110 c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. table 25-0: (1/2) parameter symbol conditions min. typ. max. unit high-level input voltage v ih1 p00 - p03, p10 - p14, p34 - p37, p40 - p47, p60 - p65, p80 - p87, p90 - p97, crxd 0.7 v dd v dd v v ih2 reset 0.8 v dd v dd v ih4 x1, x2 v dd - 0.5 v dd low-level input voltage v il1 p00 - p03, p10 - p14, p34 - p37, p40 - p47, p60 - p65, p80 - p87, p90 - p97, crxd 0 0.3 v dd v il2 reset 0.2 v dd v il4 x1, x2 0 0.4 high-level output voltage v oh1 p00 - p03, p34 - p37, p40 - p47, p60 - p67, p80 - p87, p90 - p97, ctxd v dd = 4.0 - 5.5 v i oh = -1 ma v dd - 1.0 v oh2 p20 - p27, p50 - p57 4.5 v ? ? ? ? 425 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 remark: the characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. parameter symbol conditions min. typ. max. unit high-level output leakage current i loh v out = v dd 10 a low-level output leakage current i lol v out = 0 v -10 software pull-up resistor r2 v in = 0 v 4.5 v ? table 25-0: (2/2) 426 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 pd780824a(a1), pd780826a(a1), pd780828a(a1) these specifications are only target values and may not be satisfied by mass-produced products. notes: 1. current through v dd0 , v dd1 respectively through v ss0 , v ss1 . excluded is the current through the inside pull-up resistors, through av dd /av ref , the port current and the current for the lcd split resistors. 2. cpu is operable. the other peripherals like: can controller, stepper motor c/d, timer 2, serial interfaces, sound generator and a/d converter are stopped. 3. cpu and all peripherals (except for the a/d converter) are in operating mode and pcl output is f x . 4. cpu is in halt mode and all other peripherals (except watch timer) are stopped. 5. cpu is in halt mode, but the following peripherals are active: timer 2, all other timers, serial interfaces, and pcl output is f x . remark: f x : main system clock oscillation frequency. the typical values are with respect to t a = 25 c. parameter symbol test conditions min. typ. max. unit power supply current note 1 i dd1 f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 2 5.5 12 ma f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 3 9.5 20 i dd2 f x = 8 mhz, crystal/ceramic oscillation halt mode (pcc = 04h) note 4 0.45 1.9 f x = 8 mhz, crystal/ceramic oscillation halt mode (pcc = 04h) note 5 2.5 6 i dd5 stop mode 1 1000 a 427 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 pd780824a(a1), pd780826a(a1), pd780828a(a1) lcd c/d 1/3 bias method these specifications are only target values and may not be satisfied by mass-produced products. note: the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcd ). caution: the lcd-c/d cannot be used at high temperature (t a = 110 c). the maximum temperature is t a = 85 c. parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd 3.0 v dd v lcd split resistor r lcd 51545k ? 428 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (3) pd780824a(a2), pd780826a(a2), pd780828a(a2) (t a = -40 c to +125 c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. table 25-0: (1/2) parameter symbol conditions min. typ. max. unit high-level input voltage v ih1 p00 - p03, p10 - p14, p34 - p37, p40 - p47, p60 - p65, p80 - p87, p90 - p97, crxd 0.7 v dd v dd v v ih2 reset 0.8 v dd v dd v ih4 x1, x2 v dd - 0.5 v dd low-level input voltage v il1 p00 - p03, p10 - p14, p34 - p37, p40 - p47, p60 - p65, p80 - p87, p90 - p97, crxd 0 0.3 v dd v il2 reset 0.2 v dd v il4 x1, x2 0 0.4 high-level output voltage v oh1 p00 - p03, p34 - p37, p40 - p47, p60 - p67, p80 - p87, p90 - p97, ctxd v dd = 4.0 - 5.5 v i oh = -1 ma v dd - 1.0 v oh2 p20 - p27, p50 - p57 4.5 v ? ? ? ? 429 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 remark: the characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. parameter symbol conditions min. typ. max. unit high-level output leakage current i loh v out = v dd 10 a low-level output leakage current i lol v out = 0 v -10 software pull-up resistor r2 v in = 0 v 4.5 v ? table 25-0: (2/2) 430 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 pd780824a(a2), pd780826a(a2), pd780828a(a2) these specifications are only target values and may not be satisfied by mass-produced products. notes: 1. current through v dd0 , v dd1 respectively through v ss0 , v ss1 . excluded is the current through the inside pull-up resistors, through av dd /av ref , the port current and the current for the lcd split resistors. 2. cpu is operable. the other peripherals like: can controller, stepper motor c/d, timer 2, serial interfaces, sound generator and a/d converter are stopped. 3. cpu and all peripherals (except for the a/d converter) are in operating mode and pcl output is f x . 4. cpu is in halt mode and all other peripherals (except watch timer) are stopped. 5. cpu is in halt mode, but the following peripherals are active: timer 2, all other timers, serial interfaces, and pcl output is f x . remark: f x : main system clock oscillation frequency. the typical values are with respect to t a = 25 c. parameter symbol test conditions min. typ. max. unit power supply current note 1 i dd1 f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 2 5.5 12 ma f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 3 9.5 20 i dd2 f x = 8 mhz, crystal/ceramic oscillation halt mode (pcc = 04h) note 4 0.45 1.9 f x = 8 mhz, crystal/ceramic oscillation halt mode (pcc = 04h) note 5 2.5 6 i dd5 stop mode 1 1000 a 431 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 pd780824a(a2), pd780826a(a2), pd780828a(a2) lcd c/d 1/3 bias method these specifications are only target values and may not be satisfied by mass-produced products. note: the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcd ). caution: the lcd-c/d cannot be used at high temperature (t a = 125 c). the maximum temperature is t a = 85 c. parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd 3.0 v dd v lcd split resistor r lcd 51545k ? 432 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 25.5 ac characteristics 25.5.1 basic operation (1) pd780824a(a), pd780826a(a), pd780828a(a), pd78f0828a(a) (t a = -40 c to +85 c, v dd = 4.0 to 5.5 v) notes: 1. the cycle time equals to the minimum instruction execution time. for example: 1 nop instruction corresponds to 2 cpu clock cycles (f cpu ) selected by the processor clock control register (pcc). 2. f smp2 (sampling clock) = f x /8, f x /16, f x /32, f x /64 t cy vs. v dd parameter symbol test conditions min. typ. max. unit cycle time note 1 t cy 4.0 v 433 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (2) pd780824a(a1), pd780826a(a1), pd780828a(a1) (t a = -40 c to +110 c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. notes: 1. the cycle time equals to the minimum instruction execution time. for example: 1 nop instruction corresponds to 2 cpu clock cycles (f cpu ) selected by the processor clock control register (pcc). 2. f smp2 (sampling clock) = f x /8, f x /16, f x /32, f x /64 t cy vs. v dd parameter symbol test conditions min. typ. max. unit cycle time note 1 t cy 4.0 v 434 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (3) pd780824a(a2), pd780826a(a2), pd780828a(a2) (t a = -40 c to +125 c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. notes: 1. the cycle time equals to the minimum instruction execution time. for example: 1 nop instruction corresponds to 2 cpu clock cycles (f cpu ) selected by the processor clock control register (pcc). 2. f smp2 (sampling clock) = f x /8, f x /16, f x /32, f x /64 t cy vs. v dd parameter symbol test conditions min. typ. max. unit cycle time note 1 t cy 4.0 v 435 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 25.5.2 serial interface (1) pd780824a(a), pd780826a(a), pd780828a(a), pd78f0828a(a) (t a = -40 c to +85 c, v dd = 4.0 to 5.5 v) (a) serial interface channel csi (sio30) 3-wire serial i/o mode (sck30 internal clock output) note: c is the load capacitance of so30, sck30 output line 3-wire serial i/o mode (sck30 external clock output) note: c is the load capacitance of so30, sck30 output line parameter symbol conditions min. max. unit sck30 cycle time t kcy1 1000 ns sck30 high/low-level width t kh1 , t kl1 t kcy1 /2 - 50 si30 setup time (to sck30 ) 436 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (b) serial interface channel csi (sio31) 3-wire serial i/o mode (sck31 internal clock output) note: c is the load capacitance of so30, sck31 output line 3-wire serial i/o mode (sck31 external clock output) note: c is the load capacitance of so30, sck31 output line (c) serial interface channel uart uart mode (dedicated baud rate generator output) parameter symbol conditions min. max. unit sck31 cycle time t kcy1 1000 ns sck31 high/low-level width t kh1 , t kl1 t kcy1 /2 - 50 si31 setup time (to sck31 ) 437 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (2) pd780824a(a1), pd780826a(a1), pd780828a(a1) (t a = -40 c to +110 c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. (a) serial interface channel csi (sio30) 3-wire serial i/o mode (sck30 internal clock output) note: c is the load capacitance of so30, sck30 output line 3-wire serial i/o mode (sck30 external clock output) note: c is the load capacitance of so30, sck30 output line parameter symbol conditions min. max. unit sck30 cycle time t kcy1 1000 ns sck30 high/low-level width t kh1 , t kl1 t kcy1 /2 - 50 si30 setup time (to sck30 ) 438 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (b) serial interface channel csi (sio31) 3-wire serial i/o mode (sck31 internal clock output) note: c is the load capacitance of so30, sck31 output line 3-wire serial i/o mode (sck31 external clock output) note: c is the load capacitance of so30, sck31 output line (c) serial interface channel uart uart mode (dedicated baud rate generator output) parameter symbol conditions min. max. unit sck31 cycle time t kcy1 1000 ns sck31 high/low-level width t kh1 , t kl1 t kcy1 /2 - 50 si31 setup time (to sck31 ) 439 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (3) pd780824a(a2), pd780826a(a2), pd780828a(a2) (t a = -40 c to +125 c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. (a) serial interface channel csi (sio30) 3-wire serial i/o mode (sck30 internal clock output) note: c is the load capacitance of so30, sck30 output line 3-wire serial i/o mode (sck30 external clock output) note: c is the load capacitance of so30, sck30 output line parameter symbol conditions min. max. unit sck30 cycle time t kcy1 1000 ns sck30 high/low-level width t kh1 , t kl1 t kcy1 /2 - 50 si30 setup time (to sck30 ) 440 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (b) serial interface channel csi (sio31) 3-wire serial i/o mode (sck31 internal clock output) note: c is the load capacitance of so30, sck31 output line 3-wire serial i/o mode (sck31 external clock output) note: c is the load capacitance of so30, sck31 output line (c) serial interface channel uart uart mode (dedicated baud rate generator output) parameter symbol conditions min. max. unit sck31 cycle time t kcy1 1000 ns sck31 high/low-level width t kh1 , t kl1 t kcy1 /2 - 50 si31 setup time (to sck31 ) 441 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 ac timing test points (excluding x1 input) clock timing ti timing remark: n = 2, 5 3-wire serial i/o mode / 2-wire serial i/o mode remark: m = 0, 1 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points t xl t xh 1/f x v dd ? 0.5 v 0.4 v x1 input ti20, ti21, ti22 ti50, ti51 t tihn t tiln t kcym t klm t khm sck3n si3n so3n t sikm t ksim t kso m input data output data 442 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 25.5.3 sound generator characteristics (1) pd780824a(a), pd780826a(a), pd780828a(a), pd78f0828a(a) (t a = -40 c to +85 c, v dd = 4.0 to 5.5 v) (2) pd780824a(a1), pd780826a(a1), pd780828a(a1) (t a = -40 c to +110 c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. (3) pd780824a(a2), pd780826a(a2), pd780828a(a2) (t a = -40 c to +125 c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. sound generator output timing parameter symbol conditions min. typ. max. unit sound generator input frequency f sg1 8.38 mhz sgo output rise time f r c=100 pf note 80 200 ns sgo output fall time f f c=100 pf note 80 200 ns parameter symbol conditions min. typ. max. unit sound generator input frequency f sg1 8.38 mhz sgo output rise time f r c=100 pf note 80 200 ns sgo output fall time f f c=100 pf note 80 200 ns parameter symbol conditions min. typ. max. unit sound generator input frequency f sg1 8.38 mhz sgo output rise time f r c=100 pf note 80 200 ns sgo output fall time f f c=100 pf note 80 200 ns t r t f 0.9 v dd 0.1 v dd sgo 443 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 25.5.4 meter controller / driver characteristics (1) pd780824a(a), pd780826a(a), pd780828a(a), pd78f0828a(a) (t a = -40 c to +85 c, v dd = 4.0 to 5.5 v) notes: 1. source clock of the free-running counter. 2. c is the load capacitance of the pwm output line. 3. indicates the dispersion of 16 pwm output voltages. remark: m = 1 to 4 n = 1 to 4 (2) pd780824a(a1), pd780826a(a1), pd780828a(a1) (t a = -40 c to +110 c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. notes: 1. source clock of the free-running counter. 2. c is the load capacitance of the pwm output line. 3. indicates the dispersion of 16 pwm output voltages. remark: m = 1 to 4, n = 1 to 4 the meter c/d cannot be used at high temperature (t a = 110 c). the maximum temperature is t a = 85 c. parameter symbol conditions min. typ. max. unit meter controller/driver input frequency f mc note 1 8.38 mhz pwm output rise time f r c=100 pf note 2 80 200 ns pwm output fall time f f c=100 pf note 2 80 200 ns symmetry performance note 3 ? ? ? ? ? ? ? ? 444 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (3) pd780824a(a2), pd780826a(a2), pd780828a(a2) (t a = -40 c to +125 c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. notes: 1. source clock of the free-running counter. 2. c is the load capacitance of the pwm output line. 3. indicates the dispersion of 16 pwm output voltages. remark: m = 1 to 4 n = 1 to 4 the meter c/d cannot be used at high temperature (t a = 125 c). the maximum temperature is t a = 85 c. meter controller / driver output timing parameter symbol conditions min. typ. max. unit meter controller/driver input frequency f mc note 1 8.38 mhz pwm output rise time f r c=100 pf note 2 80 200 ns pwm output fall time f f c=100 pf note 2 80 200 ns symmetry performance note 3 ? ? ? ? 445 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 25.5.5 a/d converter characteristics (1) pd780824a(a), pd780826a(a), pd780828a(a), pd78f0828a(a) (t a = -40 c to +85 c, v dd = 4.0 to 5.5 v, av ss = v ss = 0v, f x = 8 mhz) note: overall error excluding quantization ( 1/2 lsb). it is indicated as a ratio to the full-scale value. remark: f x : main system clock oscillation frequency. (2) pd780824a(a1), pd780826a(a1), pd780828a(a1) (t a = -40 c to +110 c, v dd = 4.0 to 5.5 v, av ss = v ss = 0v, f x = 8 mhz) these specifications are only target values and may not be satisfied by mass-produced products. note: overall error excluding quantization ( 1/2 lsb). it is indicated as a ratio to the full-scale value. remark: f x : main system clock oscillation frequency. parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit overall error note 0.6 % conversion time t conv 14 s analog input voltage v ian av ss av dd v reference voltage av dd / av ref av dd = v dd v dd v dd v dd av dd / av ref current i ref adcs-bit = 1 750 1500 a adcs bit = 0 0 3 parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit overall error note 1.3 % conversion time t conv 14 s analog input voltage v ian av ss av dd v reference voltage av dd / av ref av dd = v dd v dd v dd v dd av dd / av ref current i ref adcs-bit = 1 750 1500 a adcs bit = 0 0 3 446 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (3) pd780824a(a2), pd780826a(a2), pd780828a(a2) (t a = -40 c to +125 c, v dd = 4.0 to 5.5 v, av ss = v ss = 0v, f x = 8 mhz) these specifications are only target values and may not be satisfied by mass-produced products. note: overall error excluding quantization ( 1/2 lsb). it is indicated as a ratio to the full-scale value. remark: f x : main system clock oscillation frequency. parameter symbol test conditions min. typ. max. unit resolution 888bit overall error note 1.3 % conversion time t conv 14 s analog input voltage v ian av ss av dd v reference voltage av dd / av ref av dd = v dd v dd v dd v dd av dd / av ref current i ref adcs-bit = 1 750 1500 a adcs bit = 0 0 3 447 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 25.5.6 data memory stop mode low supply voltage data retention characteristics (1) pd780824a(a), pd780826a(a), pd780828a(a), pd78f0828a(a) (t a = -40 c to +85 c) note: in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register, selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible. remark: f x : main system clock oscillation frequency. (2) pd780824a(a1), pd780826a(a1), pd780828a(a1) (t a = -40 c to +110 c) these specifications are only target values and may not be satisfied by mass-produced products. note: in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register, selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible. remark: f x : main system clock oscillation frequency. parameter symbol test conditions min. typ. max. unit data retention power supply voltage v dddr 2.5 5.5 v data retention power supply current i dddr v dddr = 4.0 v 130a release signal set time t srel 0s oscillation stabilization wait time t wait release by reset 2 17 /f x ms release by interrupt note parameter symbol test conditions min. typ. max. unit data retention power supply voltage v dddr 2.5 5.5 v data retention power supply current i dddr v dddr = 4.0 v 11000a release signal set time t srel 0s oscillation stabilization wait time t wait release by reset 2 17 /f x ms release by interrupt note 448 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (3) pd780824a(a2), pd780826a(a2), pd780828a(a2) (t a = -40 c to +125 c) these specifications are only target values and may not be satisfied by mass-produced products. note: in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register, selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible. remark: f x : main system clock oscillation frequency. parameter symbol test conditions min. typ. max. unit data retention power supply voltage v dddr 2.5 5.5 v data retention power supply current i dddr v dddr = 4.0 v 1 1000 a release signal set time t srel 0s oscillation stabilization wait time t wait release by reset 2 17 /f x ms release by interrupt note 449 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) interrupt input timing reset input timing reset stop instruction execution internal reset operation halt mode operating mode t wait t srel v dddr data retension mode stop mode v dd stop instruction execution halt mode operating mode standby release signal (interrupt request) t wait t srel v dddr data retension mode stop mode v dd intp0 - intp2 t intl t inth reset t rsel 450 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 25.5.7 flash memory programming characteristics: pd78f0828a(a) (t a = 10 c to 40 c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v, v pp = 9.7 to 10.3 v) (1) basic characteristics note: operation is not guaranteed for over 20 rewrites. remark: after execution of the program command, execute the verify command and check that the writing has been completed normally. (2) serial write operation characteristics note: for maximum t ch / t cl , please make sure to finish the pulses within the time t count . parameter symbol conditions min. typ. max. unit operating frequency f x 4.0 8.38 mhz supply voltage v dd 4.0 5.5 v v ppl when v pp low-level is detected 0 0.2 v dd v v pp when v pp high-level is detected 0.8 v dd v dd 1.2 v dd v v pph when v pp high-voltage is detected and for programming 9.7 10.0 10.3 v number of rewrites c wrt 20 note times programming temperature t prg 10 +40 451 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 flash write mode setting timing reset (input) 0 v drpsr t psrrf t rfcf t cl t r t f t ch t count t dd v dd v dd v dd v ppl v pph v 0 v pp v 452 chapter 25 electrical specifications user ? s manual u16504ee1v1ud00 (3) write erase characteristics notes: 1. the recommended setting value for the step erase time is 0.2 s. 2. the prewrite time before erasure and the erase verify time (write-back time) is not included. 3. the recommended setting value for the write-back time is 50 ms. 4. write-back is executed once by the issuance of the write-back command. therefore, the number of retries must be the maximum value minus the number of commands issued. 5. recommended step write setting value is 50 s. 6. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 7. when a product is first written after shipment, "erase flash master, the time parameters that need to be downloaded from the parameter files for write/erase are automatically set. unless otherwise directed, do not change the set values. parameter symbol conditions min. typ. max. unit v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when v pp = 10 v, f x = 8.38 mhz 50 ma v pp supply current i pp when v pp = 10 v 100 ma step erase time t er note 1 0.2 s overall erase time per area t era when step erase time = 0.2 s note 2 20 s/area write-back time t wb note 3 49.4 50 50.6 ms number of write-backs per write-back command c wb when write-back time = 50 ms note 4 60 times/ write-back command number of erase/ write-backs c erwb 16 times step write time t wr note 5 48 50 52 s overall write time per word t wrw when step write time = 50 s (1 word = 1 byte) note 6 48 520 s/ word number of rewrites per area c erwr 1 erase + 1 write after erase = = 1 rewrite note 7 20 times/ area 453 user ? s manual u16504ee1v1ud00 chapter 26 package drawing remark: the shape and material of the es product is the same as the mass produced product. 80 pin plastic qfp (14 x14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. p80gc-65-8bt f 0.825 0.032 b 14.000.20 0.551 +0.009 ? 0.008 s 1.70 max. 0.067 max. m 0.17 0.007 +0.001 ? 0.003 +0.03 ? 0.07 +0.009 ? 0.008 c 14.000.20 0.551 +0.009 ? 0.008 a 17.200.20 0.6770.008 g 0.825 0.032 h 0.320.06 0.013 +0.002 ? 0.003 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) k 1.600.20 0.0630.008 l 0.800.20 0.031 +0.009 ? 0.008 n 0.10 0.004 p 1.400.10 0.0550.004 q 0.1250.075 0.0050.003 r3 ? 3 ? 3 454 user ? s manual u16504ee1v1ud00 [memo] 455 user ? s manual u16504ee1v1ud00 chapter 27 recommended soldering conditions the pd780828a subseries should be soldered and mounted under the conditions in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (iei-1207) . for soldering methods and conditions other than those recommended below, consult our sales personnel. pd780824agc(a)-xxx-8bt : 80-pin plastic qfp (14 pd780824agc(a1)-xxx-8bt : 80-pin plastic qfp (14 pd780824agc(a2)-xxx-8bt : 80-pin plastic qfp (14 pd780826agc(a)-xxx-8bt : 80-pin plastic qfp (14 pd780826agc(a1)-xxx-8bt : 80-pin plastic qfp (14 pd780826agc(a2)-xxx-8bt : 80-pin plastic qfp (14 pd780828agc(a)-xxx-8bt : 80-pin plastic qfp (14 pd780828agc(a1)-xxx-8bt : 80-pin plastic qfp (14 pd780828agc(a2)-xxx-8bt : 80-pin plastic qfp (14 pd78f0828agc(a)-8bt : 80-pin plastic qfp (14 surface mounting type soldering conditions caution: use of more than one soldering method should be avoided (except in the case of pin part heating). soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 456 user ? s manual u16504ee1v1ud00 [memo] 457 user ? s manual u16504ee1v1ud00 appendix a development tools the following development tools are available for the development of systems that employ the pd780828a subseries. figure a-1 shows the development tool configuration. support for pc98-nx series unless otherwise specified, products compatible with ibm pc/attm computers are compatible with pc98-nx series computers. when using pc98-nx series computers, refer to the explanation for ibm pc/at computers. windows (unless otherwise specified, ? windows ? means the following os). windows 95/98 windows nt version 4.0 windows 2000 458 appendix a development tools user ? s manual u16504ee1v1ud00 figure a-1: development tool configuration (a) when using the in-circuit emulator ie-78k0-ns-a remark: items in broken line boxes differ according to the development environment. see a.3.1 hardware. system simulator integrated debugger device file embedded software real-time os os debugging tool assembler package c compiler package c library source file device file language processing software flash memory write adapter in-circuit emulator power supply unit emulation probe conversion socket or conversion adapter target system host machine (pc) interface adapter, pc card interface, etc. emulation board on-chip flash memory version flash memory write environment flash programmer i/o board performance board 459 appendix a development tools user ? s manual u16504ee1v1ud00 a.1 language processing software nec software iar software a.2 flash memory writing tools ra78k/0 assembler package this assembler converts programs written in mnemonics into an object codes executa- ble with a microcontroller. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with an optional device file. 460 appendix a development tools user ? s manual u16504ee1v1ud00 a.3 debugging tools a.3.1 hardware (1) when using the in-circuit emulator ie-78k0-ns-a (2) socket details ie-78k0-ns-a in-circuit emulator the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corresponds to integrated debugger (id78k0-ns). this emulator should be used in combination with power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. ie-70000-mc-ps-b power supply unit this adapter is used for supplying power from a receptacle of 100-v to 240-v ac. eb-power fw 7301/05 power supply unit this adapter is used for supplying power from a receptable of 100 v to 240 v ac ie-70000-98-if-c interface adapter this adapter is required when using the pc-9800 series computer (except note- book type) as the ie-78k0-ns-a host machine (c bus compatible). ie-70000-cd-if-a pc card interface this is pc card and interface cable required when using notebook-type computer as the ie-78k0-ns-a host machine (pcmcia socket compatible). ie-70000-pc-if-c interface adapter this adapter is required when using the ibm pc compatible computers as the ie- 78k0-ns-a host machine (isa bus compatible). ie-70000-pci-if-a interface adapter this adapter is required when using a computer with pci bus as the ie-78k0-ns host machine. ie-78k0-ns-p04 emulation board this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. ie-780828-ns-em4 probe board this board provides the connection and buffers between the emulation board and the connector of the emulation probe. np-80gc-tq emulation probe this probe is used to connect the in-circuit emulator to a target system and is designed for use with 80-pin plastic qfp (gc-8bt type). nqpack080sb yqpack080sb yqsocket080sbf hqpack080sb conversion adapter this conversion adapter connects the np-80gc-tq to a target system board designed for a 80-pin plastic qfp (gc-8bt type). nqpack080sb socket for soldering on the target. yqpack080sb adapter socket for connecting the probe to the nqpack080sb hqpack080sb lid socket for connecting the device to the nqpack080sb yqsocket080sbf high adapter between the device to the yqpack080sb and the probe 461 appendix a development tools user ? s manual u16504ee1v1ud00 a.3.2 software sm78k0 system simulator this system simulator is used to perform debugging at c source level or assem- bler level while simulating the operation of the target system on a host machine. this simulator runs on windows. use of the sm78k0 allows the execution of application logical testing and per- formance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development effi- ciency and software quality. the sm78k0 should be used in combination with the optional device file. id78k0-ns integrated debugger (supporting in-circuit emulator ie-78k0-ns-a) this debugger is a control program to debug 78k/0 series microcontrollers. it adopts a graphical user interface, which is equivalent visually and operationally to windows or osf/motif ? . it also has an enhanced debugging function for c language programs, and thus trace results can be displayed on screen in c-lan- guage level by using the windows integration function which links a trace result with its source program, disassembled display, and memory display. in addition, by incorporating function modules such as task debugger and system perform- ance analyzer, the efficiency of debugging programs, which run on real-time oss can be improved. it should be used in combination with the optional device file. 462 user ? s manual u16504ee1v1ud00 [memo] 463 user ? s manual u16504ee1v1ud00 appendix b embedded software for efficient development and maintenance of the pd780828a subseries, the following embedded software products are available. b.1 real-time os caution: when purchasing the rx78k/0, fill in the purchase application form in advance and sign the user agreement. b.2 fuzzy inference development support system rx78k/0 real-time os rx78k/0 is a real-time os conforming with the itron specifications. tool (configura- tor) for generating nucleus of rx78k/0 and plural information tables is supplied. used in combination with an optional assembler package (ra78k/0) and device file mx78k0 os tron specification subset os. nucleus of mx78k0 is supplied. this os performs task management, event management, and time management. it controls the task exe- cution sequence for task management and selects the task to be executed next. fe9000/fe9200 fuzzy knowledge data creation tool program that supports input, edit, and evaluation (simulation) of fuzzy knowledge data (fuzzy rule and membership function). fe9200 works on windows. part number: sxxxxfe9000 (pc-9800 series) sxxxxfe9200 (ibm pc/at and compatible machines) ft9080/ft9085 program that translates fuzzy knowledge data obtained by using fuzzy knowledge. translator data creation tool into assembler source program for ra78k0. part number: sxxxxft9080 (pc-9800 series) sxxxxft9085 (ibm pc/at and compatible machines) fi78k0 program that executes fuzzy inference. executes fuzzy inference when linked with fuzzy inference module, fuzzy knowledge data translated by translator. part number: sxxxxfi78k0 (pc-9800 series, ibm pc/at and compatible machines) fd78k0 fuzzy inference debugger support software for evaluation and adjustment of fuzzy knowledge data by using in- circuit emulator and at hardware level. part number: sxxxxfd78k0 (pc-9800 series, pc/at and compatible machines) 464 user ? s manual u16504ee1v1ud00 [memo] 465 user ? s manual u16504ee1v1ud00 appendix c index numerics 16-bit timer mode control register (tmc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 16-bit timer register (tm2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8-bit timer mode control register 50 (tmc50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 8-bit timer mode control register 51 (tmc51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8-bit timer registers 50 and 51 (tm50, tm51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 a a/d conversion result register (adcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183, 194 a/d converter mode register (adm1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 analog input channel specification register (ads1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 85 asynchronous serial interface mode register (asim0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220, 226 asynchronous serial interface status register (asis0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222, 228 auxiliary carry flag (ac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 b baud rate generator control register (brgc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223, 229 bit rate prescaler register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 c can control register (canc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 can receive error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 can transmit error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 capture pulse control register (crc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 capture register 20 (cr20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 capture register 21 (cr21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 capture register 22 (cr22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 carry flag (cy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 clock output selection register (cks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 compare control register (mcmpcn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 compare register 50 and 51 (cr50, 51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 compare register n0 (mcmpn0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 compare register n1 (mcmpn1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 d d/a converter mode register (dam0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 dcan error status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 e external interrupt falling edge enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 external interrupt rising edge enable register (egp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 59 f flash self-programming mode control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 free running up counter (smcnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 g general registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 i idrec0 to idrec4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 idtx0 to idtx4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 in-service priority flag (isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 internal expansion ram size switching register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 interrupt enable flag (ie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 interrupt mask flag registers (mk0l, mk0h, mk1l) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 466 appendix c index user ? s manual u16504ee1v1ud00 interrupt request flag (adif) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 interrupt request flag registers (if0l, if0h, if1l) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356 l lcd display control register (lcdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 lcd display mode register (lcdm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 lcd timer control register (lcdtm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 m mask control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 mask identifier control register (mcon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 memory size switching register (ims) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 message count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 meter controller/driver clock register (smswi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344 o oscillation control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 oscillation stabilization time select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 p port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 port function register (pf3, pf4, pf8 and pf9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 port mode control register (pmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 port mode register (pm3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 port mode register (pm9) 211, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 port mode register 3 (pm3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 port mode register 6 (pm6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 port mode register 9 (pm9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 port mode registers (pm0, pm2 to pm6, pm8, pm9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 power-fail compare mode register (pfm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 power-fail compare threshold value register (pft) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 prescaler mode register (prm2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 priority specify flag registers (pr0l, pr0h, pr1l) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 58 processor clock control register (pcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 program status word (psw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62, 360 pull-up resistor option register (pu0, pu3, pu4, pu6, pu8, pu9) . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 pulse width measurement with free-running counter and one capture register (ti20) . . . . . . . . . . . 119 r receive buffer register (rxb0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 receive message register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 receive shift register 1 (rxs0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 redefinition control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 register bank select flags (rbs0 and rbs1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 s serial i/o shift register (sio30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 serial i/o shift register (sio31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 serial mode switch register (sioswi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209, 212, 2 14 serial operation mode register (csim30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200, 20 1 467 appendix c index user ? s manual u16504ee1v1ud00 serial operation mode register (csim30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 serial operation mode register (csim31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210, 211, 213 serial operation mode register (csim31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 sound generator amplitude register (sgam) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 sound generator buzzer control register (sgbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3 sound generator control register (sgcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 special function register (sfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66, 78 special function register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 successive approximation register (sar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 synchronization control registers 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 t the serial i/o shift register (sio31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 timer clock select register 50 (tcl50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 timer clock select register 51 (tcl51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 timer mode control register (mcntc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 transmit control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 transmit shift register 1 (txs0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 w watch timer mode register (wtm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 watchdog timer clock select register (wdcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 watchdog timer mode register (wdtm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 z zero flag (z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 468 user ? s manual u16504ee1v1ud00 469 user ? s manual u16504ee1v1ud00 appendix d revision history the following shows the revision history up to present. application portions signifies the chapter of each edition. the mark ? table 1-0: (1/2) edition no. major items revised revised sections ee1v1 correction of reference times in figure 9-2 (page 165) 9.3 caution (page 187) 12.4 description for the ims register (page 388) 23.1 notes 1 (page 388) description to table 23-2 (page 388) include caution for ims register (page 388) notes 2 (page 389) 23.2 correction of table 23-4 (page 389) change of conditions for v ih1 , v ih2 , v il1 , v il2 (pages 420, 424, 428) 25.4 470 appendix d revision history user ? s manual u16504ee1v1ud00 table 1-0: (2/2) edition no. major items revised revised sections although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-2719-5951 address north america nec electronics inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh market communication dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6465-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-6250-3583 japan nec semiconductor technical hotline i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 99.1 name company from: tel. fax facsimile message fax: +81- 44-435-9608 |
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